mb/intel/adlrvp: Add support for external clock buffer

ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7
SRCCLK's 3 will be used for CPU, the rest are for PCH. If more than 4
PCH devices are connected on the platform, an external differential
buffer chip needs to be placed at the platform level.

A mainboard designer can choose to add an external clock chip, and
select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER.

CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to
discrete buffer for further distribution to platform.

TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot.

localhost ~ # dmesg | grep mmc
[    4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA
[    5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa
[    5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB
[    5.494268]  mmcblk0: p1

Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/intel/adlrvp/Kconfig

@@ -23,12 +23,14 @@ config BOARD_INTEL_ADLRVP_P
 	select DRIVERS_UART_8250IO
 	select MAINBOARD_USES_IFD_EC_REGION
 	select SOC_INTEL_ALDERLAKE_PCH_P
+	select GEN3_EXTERNAL_CLOCK_BUFFER
 
 config BOARD_INTEL_ADLRVP_P_EXT_EC
 	select BOARD_INTEL_ADLRVP_COMMON
 	select DRIVERS_INTEL_PMC
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select SOC_INTEL_ALDERLAKE_PCH_P
+	select GEN3_EXTERNAL_CLOCK_BUFFER
 
 config BOARD_INTEL_ADLRVP_P_MCHP
 	select BOARD_INTEL_ADLRVP_COMMON
@@ -140,4 +142,20 @@ config DRIVER_TPM_SPI_BUS
 config TPM_TIS_ACPI_INTERRUPT
 	int
 	default 67 if BOARD_INTEL_ADLRVP_M_EXT_EC  # GPE0_DW2_3 (GPP_E3)
+
+config GEN3_EXTERNAL_CLOCK_BUFFER
+	bool
+	depends on SOC_INTEL_ALDERLAKE_PCH_P
+	default n
+	help
+	  Support external Gen-3 clock chip for ADL-P.
+	  `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` provides feed clock to discrete buffer
+	  for further distribution to platform. SRCCLKREQB[7:9] maps to internal
+	  SRCCLKREQB[6]. If any of them asserted, SRC buffer
+	  `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` gets enabled.
+
+config CLKSRC_FOR_EXTERNAL_BUFFER
+	depends on GEN3_EXTERNAL_CLOCK_BUFFER
+	int
+	default 6  # CLKSRC 6
 endif

src/mainboard/intel/adlrvp/romstage_fsp_params.c

@@ -24,6 +24,24 @@ static size_t get_spd_index(void)
 	return spd_index;
 }
 
+/*
+ * ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's
+ * 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are
+ * connected on the platform, an external differential buffer chip needs to be placed at
+ * the platform level.
+ *
+ * GEN3_EXTERNAL_CLOCK_BUFFER Kconfig is selected for ADL-P RVP (not applicable for
+ * ADL-M/N RVP)
+ *
+ * CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete
+ * buffer for further distribution to platform.
+ */
+static void configure_external_clksrc(FSP_M_CONFIG *m_cfg)
+{
+	for (unsigned int i = CONFIG_MAX_PCIE_CLOCK_SRC; i < CONFIG_MAX_PCIE_CLOCK_REQ; i++)
+		m_cfg->PcieClkSrcUsage[i] = CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER;
+}
+
 void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
 {
 	const struct mb_cfg *mem_config = variant_memory_params();
@@ -68,4 +86,7 @@ void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
 		die("Unknown board id = 0x%x\n", board_id);
 		break;
 	}
+
+	if (CONFIG(GEN3_EXTERNAL_CLOCK_BUFFER))
+		configure_external_clksrc(m_cfg);
 }