mb/intel/adlrvp: Add support for external clock buffer
ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are connected on the platform, an external differential buffer chip needs to be placed at the platform level. A mainboard designer can choose to add an external clock chip, and select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER. CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete buffer for further distribution to platform. TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot. localhost ~ # dmesg | grep mmc [ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA [ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa [ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB [ 5.494268] mmcblk0: p1 Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Signed-off-by: Subrata Banik <subi.banik@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -23,12 +23,14 @@ config BOARD_INTEL_ADLRVP_P
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select DRIVERS_UART_8250IO
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select DRIVERS_UART_8250IO
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select MAINBOARD_USES_IFD_EC_REGION
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select MAINBOARD_USES_IFD_EC_REGION
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select SOC_INTEL_ALDERLAKE_PCH_P
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select SOC_INTEL_ALDERLAKE_PCH_P
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select GEN3_EXTERNAL_CLOCK_BUFFER
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config BOARD_INTEL_ADLRVP_P_EXT_EC
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config BOARD_INTEL_ADLRVP_P_EXT_EC
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select BOARD_INTEL_ADLRVP_COMMON
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select BOARD_INTEL_ADLRVP_COMMON
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select DRIVERS_INTEL_PMC
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select DRIVERS_INTEL_PMC
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select INTEL_LPSS_UART_FOR_CONSOLE
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select INTEL_LPSS_UART_FOR_CONSOLE
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select SOC_INTEL_ALDERLAKE_PCH_P
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select SOC_INTEL_ALDERLAKE_PCH_P
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select GEN3_EXTERNAL_CLOCK_BUFFER
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config BOARD_INTEL_ADLRVP_P_MCHP
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config BOARD_INTEL_ADLRVP_P_MCHP
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select BOARD_INTEL_ADLRVP_COMMON
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select BOARD_INTEL_ADLRVP_COMMON
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@ -140,4 +142,20 @@ config DRIVER_TPM_SPI_BUS
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config TPM_TIS_ACPI_INTERRUPT
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config TPM_TIS_ACPI_INTERRUPT
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int
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int
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default 67 if BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3)
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default 67 if BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3)
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config GEN3_EXTERNAL_CLOCK_BUFFER
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bool
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depends on SOC_INTEL_ALDERLAKE_PCH_P
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default n
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help
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Support external Gen-3 clock chip for ADL-P.
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`CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` provides feed clock to discrete buffer
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for further distribution to platform. SRCCLKREQB[7:9] maps to internal
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SRCCLKREQB[6]. If any of them asserted, SRC buffer
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`CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` gets enabled.
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config CLKSRC_FOR_EXTERNAL_BUFFER
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depends on GEN3_EXTERNAL_CLOCK_BUFFER
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int
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default 6 # CLKSRC 6
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endif
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endif
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@ -24,6 +24,24 @@ static size_t get_spd_index(void)
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return spd_index;
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return spd_index;
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}
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}
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/*
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* ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's
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* 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are
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* connected on the platform, an external differential buffer chip needs to be placed at
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* the platform level.
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*
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* GEN3_EXTERNAL_CLOCK_BUFFER Kconfig is selected for ADL-P RVP (not applicable for
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* ADL-M/N RVP)
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*
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* CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete
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* buffer for further distribution to platform.
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*/
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static void configure_external_clksrc(FSP_M_CONFIG *m_cfg)
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{
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for (unsigned int i = CONFIG_MAX_PCIE_CLOCK_SRC; i < CONFIG_MAX_PCIE_CLOCK_REQ; i++)
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m_cfg->PcieClkSrcUsage[i] = CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER;
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}
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void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
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void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
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{
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{
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const struct mb_cfg *mem_config = variant_memory_params();
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const struct mb_cfg *mem_config = variant_memory_params();
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@ -68,4 +86,7 @@ void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
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die("Unknown board id = 0x%x\n", board_id);
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die("Unknown board id = 0x%x\n", board_id);
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break;
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break;
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}
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}
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if (CONFIG(GEN3_EXTERNAL_CLOCK_BUFFER))
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configure_external_clksrc(m_cfg);
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}
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}
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