lenovo/t520: Use native LVDS gfx init
As introduced in:
1783a3c
ivybridge: LVDS gfx init.
The panel on the T520 is a LP156WD1 40 pin LVDS (2 ch, 6-bit).
Tx parameters derived from datasheet table.
Change-Id: Ib733836e3233a7f14a79f36a27ed36b638e837f5
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7100
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
This commit is contained in:
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df5a91dd0e
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@ -15,6 +15,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_RESUME
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select HAVE_SMI_HANDLER
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select INTEL_INT15
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select EARLY_CBMEM_INIT
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select VGA
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select INTEL_EDID
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
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select SANDYBRIDGE_LVDS
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# Workaround for EC/KBC IRQ1.
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select SERIRQ_CONTINUOUS_MODE
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@ -5,11 +5,17 @@ chip northbridge/intel/sandybridge
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# Enable Panel as LVDS and configure power delays
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register "gpu_panel_port_select" = "0" # LVDS
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register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
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register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
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register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
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register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
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register "gpu_panel_power_cycle_delay" = "5"
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register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms
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register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms
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register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
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register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
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register "gfx.use_spread_spectrum_clock" = "1"
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register "gfx.lvds_dual_channel" = "1"
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register "gfx.link_frequency_270_mhz" = "1"
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register "gfx.lvds_num_lanes" = "4"
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register "gpu_cpu_backlight" = "0x1155"
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register "gpu_pch_backlight" = "0x06100610"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA988B
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