mainboard/compulab: add support for CompuLab Intense-PC
Add coreboot support for CompuLab Intense-PC (Ivy Bridge) Modifications: - Memory SPDs have been fixed to detect both installed SODIMM modules - Full-height Mini-PCIe slot defaults to PCIe mode - mSATA can be chosen instead of mPCIe via Kconfig option ENABLE_MSATA Tested (Xubuntu 17.10/Linux 4.13 where applicable): - 2+2GB DDR3-1600 SODIMMs pass memtest - 4+4GB DDR3-1600 SODIMMs pass memtest - 4+8GB DDR3-1333 SODIMMs pass memtest - 8+8GB DDR3-1333 SODIMMs pass memtest - Booting via USB working (with no SATA HDD present) - Booting to main SATA HDD working - DisplayPort and HDMI output working for coreboot init (*requires* VGA BIOS) - DisplayPort and HDMI dual-head working in Linux - Mini-PCIe devices (half/full-height) detected in Linux - mSATA working (when chosen using ENABLE_MSATA) - Onboard Intel 82579 GbE working - Secondary Realtek 8111 GbE working - Rear eSATA ports working - Onboard analog audio output working - HDMI audio output working - USB 3.0 working - Suspend to RAM (S3) working, but not tested extensively - Mini PCIe WiFi - FACE module FM-4USB (4 USB 2.0 ports) Disabled/unsupported: - TPM (BTO option, not included in base config) - FACE modules: - FM-USB3 (USB 3.0/mSATA) NOT SUPPORTED/TESTED - FM-SER (serial) NOT SUPPORTED/TESTED - FM-XTDEU2/4 (LAN) NOT SUPPORTED/TESTED - FM-XTDE4U2/4 (Quad LAN) NOT SUPPORTED/TESTED - FM-XTDM2 (dual mPCIe) NOT SUPPORTED/TESTED - FM-VC (video capture) NOT SUPPORTED/TESTED - FM-POE (Quad LAN w/PoE) NOT SUPPORTED/TESTED Not tested: - RS-232 Product information: http://www.fit-pc.com/web/products/intense-pc/ Change-Id: I741b0b2f87eb9147c375b405a5b6989a10c7ad0a Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/22210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Hal Martin
Stefan Reinauer
parent
59bd6a4d60
commit
de7f8d3a19
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@ -0,0 +1,16 @@
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if VENDOR_COMPULAB
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choice
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prompt "Mainboard model"
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source "src/mainboard/compulab/*/Kconfig.name"
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endchoice
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source "src/mainboard/compulab/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "CompuLab"
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endif # VENDOR_COMPULAB
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@ -0,0 +1,2 @@
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config VENDOR_COMPULAB
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bool "CompuLab"
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@ -0,0 +1,69 @@
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if BOARD_COMPULAB_INTENSE_PC
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select CPU_INTEL_SOCKET_FCBGA1023
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select EC_ACPI
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_INT15
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select SANDYBRIDGE_IVYBRIDGE_LVDS
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_C216
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select SYSTEM_TYPE_LAPTOP
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select USE_NATIVE_RAMINIT
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config HAVE_IFD_BIN
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bool
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default n
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config HAVE_ME_BIN
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bool
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default n
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config HAVE_GBE_BIN
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bool
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default n
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config MAINBOARD_DIR
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string
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default compulab/intense_pc
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config MAINBOARD_PART_NUMBER
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string
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default "Intense-PC"
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config VGA_BIOS_ID
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string
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default "8086,0166"
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x7270
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x8086
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config DRAM_RESET_GATE_GPIO # FIXME: check this
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int
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default 60
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config MAX_CPUS
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int
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default 8
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config USBDEBUG_HCD_INDEX # FIXME: check this
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int
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default 2
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config ENABLE_MSATA # enable mSATA instead of mPCIe on full height slot
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bool "Use full-height mini-PCIe for mSATA"
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default n
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endif
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@ -0,0 +1,2 @@
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config BOARD_COMPULAB_INTENSE_PC
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bool "Intense-PC"
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romstage-y += gpio.c
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ramstage-y += acpi_tables.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Hal Martin <hal.martin@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Device(EC)
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{
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Name (_HID, EISAID("PNP0C09"))
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Name (_UID, 0)
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Name (_GPE, 23)
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/* FIXME: EC support */
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}
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Hal Martin <hal.martin@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Method(_WAK,1)
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{
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/* FIXME: EC support */
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Return(Package(){0,0})
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}
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Method(_PTS,1)
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{
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/* FIXME: EC support */
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}
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@ -0,0 +1,16 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Hal Martin <hal.martin@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <drivers/pc80/pc/ps2_controller.asl>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Vladimir Serbinenko
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* Copyright (C) 2017 Hal Martin <hal.martin@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/bd82x6x/nvs.h>
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/* FIXME: check this function. */
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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gnvs->tcrt = 100;
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gnvs->tpsv = 90;
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}
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Vendor name: CompuLab
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Board name: Intense-PC
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Category: laptop
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ROM package: SOIC-16
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: n
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2017 Hal Martin <hal.martin@gmail.com>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
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register "gfx.link_frequency_270_mhz" = "1"
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register "gfx.ndid" = "3"
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register "gfx.use_spread_spectrum_clock" = "0"
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register "gpu_cpu_backlight" = "0x00000000"
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register "gpu_dp_b_hotplug" = "4"
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register "gpu_dp_c_hotplug" = "4"
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register "gpu_dp_d_hotplug" = "4"
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register "gpu_panel_port_select" = "0"
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register "gpu_panel_power_backlight_off_delay" = "0"
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register "gpu_panel_power_backlight_on_delay" = "0"
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register "gpu_panel_power_cycle_delay" = "4"
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register "gpu_panel_power_down_delay" = "0"
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register "gpu_panel_power_up_delay" = "0"
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register "gpu_pch_backlight" = "0x00000000"
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device cpu_cluster 0x0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0x0 on
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end
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end
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chip cpu/intel/model_206ax # FIXME: check all registers
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register "c1_acpower" = "1"
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register "c1_battery" = "1"
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register "c2_acpower" = "3"
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register "c2_battery" = "3"
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register "c3_acpower" = "5"
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register "c3_battery" = "5"
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device lapic 0xacac off
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end
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end
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end
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device domain 0x0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "docking_supported" = "1"
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register "gen1_dec" = "0x0000164d"
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register "gen2_dec" = "0x000c0681"
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register "gen3_dec" = "0x000406f1"
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register "gen4_dec" = "0x000c06a1"
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register "gpi7_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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# Intense PC SATA portmap:
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# Port 0: internal 2.5" bay
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# Port 1: optional FACE module
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# Port 2: rear eSATA
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# Port 3: rear eSATA
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# Port 4: mSATA
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# Port 5: optional FACE module
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# enable ALL ports (FACE module REQUIRED for ports 1&5)
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register "sata_port_map" = "0x3f"
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# enable ONLY ports present on stock MintBox/Intense PC
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#register "sata_port_map" = "0x1d"
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register "superspeed_capable_ports" = "0x0000000f"
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_switchable_ports" = "0x0000000f"
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register "spi_uvscc" = "0x2005"
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register "spi_lvscc" = "0x2005"
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# USB 3.0 Controller
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device pci 14.0 on
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subsystemid 0x8086 0x7270
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end
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# Management Engine Interface 1
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device pci 16.0 off
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end
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# Management Engine Interface 2
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device pci 16.1 off
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end
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# Management Engine IDE-R
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device pci 16.2 off
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end
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# Management Engine KT
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device pci 16.3 off
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end
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# Intel Gigabit Ethernet
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device pci 19.0 on
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end
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# USB2 EHCI #2
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device pci 1a.0 on
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subsystemid 0x8086 0x7270
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end
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# High Definition Audio Audio controller
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device pci 1b.0 on
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subsystemid 0x8086 0x7270
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end
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# PCIe Port #1
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device pci 1c.0 on
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subsystemid 0x8086 0x7270
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end
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# PCIe Port #2
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device pci 1c.1 on
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subsystemid 0x8086 0x7270
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end
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# PCIe Port #3
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device pci 1c.2 on
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subsystemid 0x8086 0x7270
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end
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# PCIe Port #4
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device pci 1c.3 off
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end
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# PCIe Port #5
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device pci 1c.4 on
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subsystemid 0x8086 0x7270
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end
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# PCIe Port #6
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device pci 1c.5 off
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end
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# PCIe Port #7
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device pci 1c.6 off
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end
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# PCIe Port #8
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device pci 1c.7 off
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end
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# USB2 EHCI #1
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device pci 1d.0 on
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subsystemid 0x8086 0x7270
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end
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# PCI bridge
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device pci 1e.0 off
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end
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# LPC bridge PCI-LPC bridge
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device pci 1f.0 on
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subsystemid 0x8086 0x7270
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end
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# SATA Controller 1
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device pci 1f.2 on
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subsystemid 0x8086 0x7270
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end
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# SMBus
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device pci 1f.3 on
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subsystemid 0x8086 0x7270
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end
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# SATA Controller 2
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device pci 1f.5 off
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end
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# Thermal Unsupported PCI device 8086:1e24
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device pci 1f.6 on
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subsystemid 0x8086 0x7270
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end
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end
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# Host bridge Host bridge
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device pci 00.0 on
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subsystemid 0x8086 0x2010
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end
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# PCIe Bridge for discrete graphics PCI device 8086:0151
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device pci 01.0 on
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subsystemid 0x8086 0x2010
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end
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# Internal graphics VGA controller
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device pci 02.0 on
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subsystemid 0x8086 0x2211
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end
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# Unsupported PCI device 8086:0155
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device pci 01.1 on
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subsystemid 0x8086 0x2010
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end
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end
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end
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@ -0,0 +1,46 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Hal Martin <hal.martin@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
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#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
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#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x03, // DSDT revision: ACPI v3.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20141018 // OEM revision
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)
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{
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// Some generic macros
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#include "acpi/platform.asl"
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#include <cpu/intel/model_206ax/acpi/cpu.asl>
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#include <southbridge/intel/bd82x6x/acpi/platform.asl>
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/* global NVS and variables. */
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#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
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#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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#include <southbridge/intel/bd82x6x/acpi/pch.asl>
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#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
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}
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}
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}
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@ -0,0 +1,219 @@
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/*
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* This file is part of the coreboot project.
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||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
.gpio2 = GPIO_MODE_GPIO,
|
||||
.gpio3 = GPIO_MODE_GPIO,
|
||||
.gpio4 = GPIO_MODE_GPIO,
|
||||
.gpio5 = GPIO_MODE_GPIO,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio9 = GPIO_MODE_NATIVE,
|
||||
.gpio10 = GPIO_MODE_NATIVE,
|
||||
.gpio11 = GPIO_MODE_GPIO,
|
||||
.gpio12 = GPIO_MODE_NATIVE,
|
||||
.gpio13 = GPIO_MODE_NATIVE,
|
||||
.gpio14 = GPIO_MODE_GPIO,
|
||||
.gpio15 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_NATIVE,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio18 = GPIO_MODE_NATIVE,
|
||||
.gpio19 = GPIO_MODE_NATIVE,
|
||||
.gpio20 = GPIO_MODE_NATIVE,
|
||||
.gpio21 = GPIO_MODE_NATIVE,
|
||||
.gpio22 = GPIO_MODE_NATIVE,
|
||||
.gpio23 = GPIO_MODE_NATIVE,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio25 = GPIO_MODE_NATIVE,
|
||||
.gpio26 = GPIO_MODE_NATIVE,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
.gpio29 = GPIO_MODE_GPIO,
|
||||
.gpio30 = GPIO_MODE_NATIVE,
|
||||
.gpio31 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio2 = GPIO_DIR_INPUT,
|
||||
.gpio3 = GPIO_DIR_INPUT,
|
||||
.gpio4 = GPIO_DIR_INPUT,
|
||||
.gpio5 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio8 = GPIO_DIR_OUTPUT,
|
||||
.gpio11 = GPIO_DIR_INPUT,
|
||||
.gpio14 = GPIO_DIR_INPUT,
|
||||
.gpio15 = GPIO_DIR_INPUT,
|
||||
.gpio17 = GPIO_DIR_INPUT,
|
||||
.gpio24 = GPIO_DIR_OUTPUT,
|
||||
.gpio27 = GPIO_DIR_OUTPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
.gpio29 = GPIO_DIR_OUTPUT,
|
||||
.gpio31 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
#if IS_ENABLED(CONFIG_ENABLE_MSATA)
|
||||
.gpio8 = GPIO_LEVEL_LOW,
|
||||
#else
|
||||
.gpio8 = GPIO_LEVEL_HIGH,
|
||||
#endif
|
||||
.gpio24 = GPIO_LEVEL_LOW,
|
||||
.gpio27 = GPIO_LEVEL_LOW,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
.gpio29 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
.gpio24 = GPIO_RESET_RSMRST,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio1 = GPIO_INVERT,
|
||||
.gpio7 = GPIO_INVERT,
|
||||
.gpio14 = GPIO_INVERT,
|
||||
.gpio15 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_NATIVE,
|
||||
.gpio33 = GPIO_MODE_NATIVE,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_NATIVE,
|
||||
.gpio36 = GPIO_MODE_NATIVE,
|
||||
.gpio37 = GPIO_MODE_GPIO,
|
||||
.gpio38 = GPIO_MODE_NATIVE,
|
||||
.gpio39 = GPIO_MODE_NATIVE,
|
||||
.gpio40 = GPIO_MODE_NATIVE,
|
||||
.gpio41 = GPIO_MODE_NATIVE,
|
||||
.gpio42 = GPIO_MODE_NATIVE,
|
||||
.gpio43 = GPIO_MODE_NATIVE,
|
||||
.gpio44 = GPIO_MODE_NATIVE,
|
||||
.gpio45 = GPIO_MODE_NATIVE,
|
||||
.gpio46 = GPIO_MODE_GPIO,
|
||||
.gpio47 = GPIO_MODE_NATIVE,
|
||||
.gpio48 = GPIO_MODE_NATIVE,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_GPIO,
|
||||
.gpio51 = GPIO_MODE_GPIO,
|
||||
.gpio52 = GPIO_MODE_GPIO,
|
||||
.gpio53 = GPIO_MODE_GPIO,
|
||||
.gpio54 = GPIO_MODE_GPIO,
|
||||
.gpio55 = GPIO_MODE_GPIO,
|
||||
.gpio56 = GPIO_MODE_NATIVE,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
.gpio58 = GPIO_MODE_NATIVE,
|
||||
.gpio59 = GPIO_MODE_NATIVE,
|
||||
.gpio60 = GPIO_MODE_GPIO,
|
||||
.gpio61 = GPIO_MODE_NATIVE,
|
||||
.gpio62 = GPIO_MODE_NATIVE,
|
||||
.gpio63 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio34 = GPIO_DIR_OUTPUT,
|
||||
.gpio37 = GPIO_DIR_OUTPUT,
|
||||
.gpio46 = GPIO_DIR_OUTPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio50 = GPIO_DIR_OUTPUT,
|
||||
.gpio51 = GPIO_DIR_OUTPUT,
|
||||
.gpio52 = GPIO_DIR_OUTPUT,
|
||||
.gpio53 = GPIO_DIR_OUTPUT,
|
||||
.gpio54 = GPIO_DIR_OUTPUT,
|
||||
.gpio55 = GPIO_DIR_OUTPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
.gpio60 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio34 = GPIO_LEVEL_HIGH,
|
||||
.gpio37 = GPIO_LEVEL_LOW,
|
||||
.gpio46 = GPIO_LEVEL_HIGH,
|
||||
.gpio50 = GPIO_LEVEL_HIGH,
|
||||
.gpio51 = GPIO_LEVEL_LOW,
|
||||
.gpio52 = GPIO_LEVEL_HIGH,
|
||||
.gpio53 = GPIO_LEVEL_HIGH,
|
||||
.gpio54 = GPIO_LEVEL_HIGH,
|
||||
.gpio55 = GPIO_LEVEL_LOW,
|
||||
.gpio60 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_NATIVE,
|
||||
.gpio65 = GPIO_MODE_NATIVE,
|
||||
.gpio66 = GPIO_MODE_GPIO,
|
||||
.gpio67 = GPIO_MODE_GPIO,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_NATIVE,
|
||||
.gpio71 = GPIO_MODE_NATIVE,
|
||||
.gpio72 = GPIO_MODE_NATIVE,
|
||||
.gpio73 = GPIO_MODE_NATIVE,
|
||||
.gpio74 = GPIO_MODE_NATIVE,
|
||||
.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio66 = GPIO_DIR_OUTPUT,
|
||||
.gpio67 = GPIO_DIR_INPUT,
|
||||
.gpio68 = GPIO_DIR_OUTPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
.gpio66 = GPIO_LEVEL_LOW,
|
||||
.gpio68 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
* Copyright (C) 2017 Hal Martin <hal.martin@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0888, /* Codec Vendor / Device ID: Realtek */
|
||||
0x10ec0888, /* Subsystem ID */
|
||||
|
||||
0x0000000f, /* Number of 4 dword sets */
|
||||
/* NID 0x01: Subsystem ID. */
|
||||
AZALIA_SUBVENDOR(0x0, 0x10ec0888),
|
||||
|
||||
/* NID 0x11. */
|
||||
AZALIA_PIN_CFG(0x0, 0x11, 0x411110f0),
|
||||
|
||||
/* NID 0x12. */
|
||||
AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
|
||||
|
||||
/* NID 0x14. */
|
||||
AZALIA_PIN_CFG(0x0, 0x14, 0x01214120),
|
||||
|
||||
/* NID 0x15. */
|
||||
AZALIA_PIN_CFG(0x0, 0x15, 0x411111f0),
|
||||
|
||||
/* NID 0x16. */
|
||||
AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0),
|
||||
|
||||
/* NID 0x17. */
|
||||
AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
|
||||
|
||||
/* NID 0x18. */
|
||||
AZALIA_PIN_CFG(0x0, 0x18, 0x01a19131),
|
||||
|
||||
/* NID 0x19. */
|
||||
AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
|
||||
|
||||
/* NID 0x1a. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
|
||||
|
||||
/* NID 0x1b. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
|
||||
|
||||
/* NID 0x1c. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),
|
||||
|
||||
/* NID 0x1d. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1d, 0x411111f0),
|
||||
|
||||
/* NID 0x1e. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1e, 0x014421f0),
|
||||
|
||||
/* NID 0x1f. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1f, 0x01c421f0),
|
||||
0x80862806, /* Codec Vendor / Device ID: Intel */
|
||||
0x80860101, /* Subsystem ID */
|
||||
|
||||
0x00000004, /* Number of 4 dword sets */
|
||||
/* NID 0x01: Subsystem ID. */
|
||||
AZALIA_SUBVENDOR(0x3, 0x80860101),
|
||||
|
||||
/* NID 0x05. */
|
||||
AZALIA_PIN_CFG(0x3, 0x05, 0x58560010),
|
||||
|
||||
/* NID 0x06. */
|
||||
AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
|
||||
|
||||
/* NID 0x07. */
|
||||
AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Hal Martin <hal.martin@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include <drivers/intel/gma/int15.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <ec/acpi/ec.h>
|
||||
#include <console/console.h>
|
||||
#include <pc80/keyboard.h>
|
||||
|
||||
static void mainboard_init(device_t dev)
|
||||
{
|
||||
/* FIXME: trim this down or remove if necessary */
|
||||
{
|
||||
int i;
|
||||
const u8 dmp[256] = {
|
||||
/* 00 */ 0x00, 0x28, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 08 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 18 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 28 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x36, 0x3c, 0x6e,
|
||||
/* 30 */ 0xb8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 38 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
|
||||
/* 48 */ 0xff, 0x42, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 58 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 68 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x41,
|
||||
/* 70 */ 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
|
||||
/* 78 */ 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
|
||||
/* 80 */ 0x28, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 88 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 98 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* a8 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* b8 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* c0 */ 0x00, 0x00, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
|
||||
/* c8 */ 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
|
||||
/* d0 */ 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
|
||||
/* d8 */ 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
|
||||
/* e0 */ 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
|
||||
/* e8 */ 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
|
||||
/* f0 */ 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
|
||||
/* f8 */ 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
|
||||
};
|
||||
|
||||
printk(BIOS_DEBUG, "Replaying EC dump ...");
|
||||
for (i = 0; i < 256; i++)
|
||||
ec_write (i, dmp[i]);
|
||||
printk(BIOS_DEBUG, "done\n");
|
||||
}
|
||||
pc_keyboard_init(NO_AUX_DEVICE);
|
||||
}
|
||||
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
dev->ops->init = mainboard_init;
|
||||
|
||||
/* FIXME: fix those values*/
|
||||
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
||||
GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Hal Martin <hal.martin@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <lib.h>
|
||||
#include <arch/io.h>
|
||||
#include "northbridge/intel/sandybridge/raminit_native.h"
|
||||
|
||||
void pch_enable_lpc(void)
|
||||
{
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x0000164d);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0681);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000406f1);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
|
||||
}
|
||||
|
||||
void rcba_config(void)
|
||||
{
|
||||
/* Disable devices. */
|
||||
RCBA32(0x3414) = 0x00000000;
|
||||
RCBA32(0x3418) = 0x16e81fe3;
|
||||
|
||||
}
|
||||
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
{ 1, 1, 0 },
|
||||
{ 1, 1, 0 },
|
||||
{ 1, 1, 1 },
|
||||
{ 1, 1, 1 },
|
||||
{ 1, 0, 2 },
|
||||
{ 1, 0, 2 },
|
||||
{ 1, 0, 3 },
|
||||
{ 1, 0, 3 },
|
||||
{ 1, 1, 4 },
|
||||
{ 1, 1, 4 },
|
||||
{ 1, 0, 5 },
|
||||
{ 1, 0, 5 },
|
||||
{ 1, 0, 6 },
|
||||
{ 1, 0, 6 },
|
||||
};
|
||||
|
||||
void mainboard_early_init(int s3resume)
|
||||
{
|
||||
}
|
||||
|
||||
void mainboard_config_superio(void)
|
||||
{
|
||||
}
|
||||
|
||||
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
||||
{
|
||||
read_spd(&spd[0], 0x50, id_only);
|
||||
read_spd(&spd[2], 0x52, id_only);
|
||||
}
|
||||
Loading…
Reference in New Issue