diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c
index 64b462fb8c..36aa1498b5 100644
--- a/src/mainboard/intel/dg43gt/romstage.c
+++ b/src/mainboard/intel/dg43gt/romstage.c
@@ -60,7 +60,10 @@ static void ich10_enable_lpc(void)
 {
 	/* Configure serial IRQs.*/
 	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-	pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f);
+	pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
+			   | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
+			   | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			   | COMB_LPC_EN | COMA_LPC_EN);
 	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0xfc0601);
 	pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xfc0291);
 	pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0);
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 2e2d719129..3c09746f81 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -99,6 +99,16 @@
 #define D31F0_PIRQH_ROUT	0x6b
 #define D31F0_LPC_IODEC		0x80
 #define D31F0_LPC_EN		0x82
+#define   CNF2_LPC_EN		(1 << 13) /* 0x4e/0x4f */
+#define   CNF1_LPC_EN		(1 << 12) /* 0x2e/0x2f */
+#define   MC_LPC_EN		(1 << 11) /* 0x62/0x66 */
+#define   KBC_LPC_EN		(1 << 10) /* 0x60/0x64 */
+#define   GAMEH_LPC_EN		(1 << 9)  /* 0x208/0x20f */
+#define   GAMEL_LPC_EN		(1 << 8)  /* 0x200/0x207 */
+#define   FDD_LPC_EN		(1 << 3)  /* LPC_IO_DEC[12] */
+#define   LPT_LPC_EN		(1 << 2)  /* LPC_IO_DEC[9:8] */
+#define   COMB_LPC_EN		(1 << 1)  /* LPC_IO_DEC[6:4] */
+#define   COMA_LPC_EN		(1 << 0)  /* LPC_IO_DEC[2:0] */
 #define D31F0_GEN1_DEC		0x84
 #define D31F0_GEN2_DEC		0x88
 #define D31F0_GEN3_DEC		0x8c