cpu/x86/lapic: Replace LOCAL_APIC_ADDR references

Note that there are assumptions about LAPIC MMIO location
in both AMD and Intel sources in coreboot proper.

Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/x86/cpu.c

@@ -340,8 +340,3 @@ int cpu_index(void)
 	}
 	return -1;
 }
-
-uintptr_t cpu_get_lapic_addr(void)
-{
-	return LOCAL_APIC_ADDR;
-}

src/arch/x86/include/arch/smp/mpspec.h

@@ -224,7 +224,7 @@ struct mp_exten_compatibility_address_space {
 	 */
 } __packed;
 
-void mptable_init(struct mp_config_table *mc, u32 lapic_addr);
+void mptable_init(struct mp_config_table *mc);
 void *smp_next_mpc_entry(struct mp_config_table *mc);
 void *smp_next_mpe_entry(struct mp_config_table *mc);
 

src/arch/x86/mpspec.c

@@ -6,13 +6,15 @@
 #include <arch/smp/mpspec.h>
 #include <string.h>
 #include <arch/cpu.h>
+#include <cpu/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <drivers/generic/ioapic/chip.h>
 
 /* Initialize the specified "mc" struct with initial values. */
-void mptable_init(struct mp_config_table *mc, u32 lapic_addr)
+void mptable_init(struct mp_config_table *mc)
 {
 	int i;
+	u32 lapic_addr = cpu_get_lapic_addr();
 
 	memset(mc, 0, sizeof(*mc));
 
@@ -533,7 +535,7 @@ unsigned long __weak write_smp_table(unsigned long addr)
 	v = smp_write_floating_table(addr, 0);
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LOCAL_APIC_ADDR);
+	mptable_init(mc);
 
 	smp_write_processors(mc);
 

src/cpu/x86/lapic/lapic.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/lapic_def.h>
 #include <cpu/x86/msr.h>
@@ -25,6 +26,11 @@ void disable_lapic(void)
 	wrmsr(LAPIC_BASE_MSR, msr);
 }
 
+uintptr_t cpu_get_lapic_addr(void)
+{
+	return LAPIC_DEFAULT_BASE;
+}
+
 /* See if I need to initialize the local APIC */
 static int need_lapic_init(void)
 {

src/cpu/x86/smm/smmhandler.S

@@ -126,8 +126,9 @@ untampered_lapic:
 	movw	%ax, %fs
 	movw	%ax, %gs
 
+	/* FIXME: Incompatible with X2APIC_SUPPORT. */
 	/* Get this CPU's LAPIC ID */
-	movl	$(LOCAL_APIC_ADDR | LAPIC_ID), %esi
+	movl	$(LAPIC_DEFAULT_BASE | LAPIC_ID), %esi
 	movl	(%esi), %ecx
 	shr	$24, %ecx
 

src/include/cpu/x86/lapic_def.h

@@ -9,12 +9,7 @@
 	(LAPIC_BASE_MSR_X2APIC_MODE | LAPIC_BASE_MSR_ENABLE)
 #define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000
 
-#ifndef LOCAL_APIC_ADDR
-#define LOCAL_APIC_ADDR 0xfee00000
-#endif
-#ifndef LAPIC_DEFAULT_BASE
-#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR
-#endif
+#define LAPIC_DEFAULT_BASE 0xfee00000
 
 #define LAPIC_ID		0x020
 #define LAPIC_LVR	0x030

src/mainboard/apple/macbook21/mptable.c

@@ -11,7 +11,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LOCAL_APIC_ADDR);
+	mptable_init(mc);
 
 	smp_write_processors(mc);
 

src/mainboard/asus/a88xm-e/mptable.c

@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LOCAL_APIC_ADDR);
+	mptable_init(mc);
 	memcpy(mc->mpc_oem, "AMD     ", 8);
 
 	smp_write_processors(mc);

src/mainboard/asus/p2b/variants/p2b-d/mptable.c

@@ -10,7 +10,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LOCAL_APIC_ADDR);
+	mptable_init(mc);
 
 	smp_write_processors(mc);
 

src/mainboard/asus/p2b/variants/p2b-ds/mptable.c

@@ -10,7 +10,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LOCAL_APIC_ADDR);
+	mptable_init(mc);
 
 	smp_write_processors(mc);
 

src/mainboard/emulation/qemu-i440fx/northbridge.c

@@ -155,7 +155,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 	/* Reserve space for the LAPIC.  There's one in every processor, but
 	 * the space only needs to be reserved once, so we do it here. */
 	res = new_resource(dev, 3);
-	res->base = LOCAL_APIC_ADDR;
+	res->base = cpu_get_lapic_addr();
 	res->size = 0x10000UL;
 	res->limit = 0xffffffffUL;
 	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |

src/mainboard/getac/p470/mptable.c

@@ -11,7 +11,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LOCAL_APIC_ADDR);
+	mptable_init(mc);
 
 	smp_write_processors(mc);
 

src/mainboard/ibase/mb899/mptable.c

@@ -14,7 +14,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LOCAL_APIC_ADDR);
+	mptable_init(mc);
 
 	smp_write_processors(mc);
 

src/mainboard/intel/d945gclf/mptable.c

@@ -11,7 +11,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LOCAL_APIC_ADDR);
+	mptable_init(mc);
 
 	smp_write_processors(mc);
 

src/mainboard/kontron/986lcd-m/mptable.c

@@ -13,7 +13,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LOCAL_APIC_ADDR);
+	mptable_init(mc);
 
 	smp_write_processors(mc);
 

src/mainboard/lenovo/t60/mptable.c

@@ -11,7 +11,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LOCAL_APIC_ADDR);
+	mptable_init(mc);
 
 	smp_write_processors(mc);
 

src/mainboard/lenovo/x60/mptable.c

@@ -11,7 +11,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LOCAL_APIC_ADDR);
+	mptable_init(mc);
 
 	smp_write_processors(mc);
 

src/mainboard/roda/rk886ex/mptable.c

@@ -11,7 +11,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LOCAL_APIC_ADDR);
+	mptable_init(mc);
 
 	smp_write_processors(mc);
 

src/soc/amd/cezanne/data_fabric.c

@@ -37,7 +37,7 @@ void data_fabric_set_mmio_np(void)
 	int reg;
 	uint32_t base, limit, ctrl;
 	const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT;
-	const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT;
+	const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT;
 
 	data_fabric_print_mmio_conf();
 

src/soc/amd/picasso/data_fabric.c

@@ -37,7 +37,7 @@ void data_fabric_set_mmio_np(void)
 	int reg;
 	uint32_t base, limit, ctrl;
 	const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT;
-	const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT;
+	const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT;
 
 	data_fabric_print_mmio_conf();
 

src/soc/amd/stoneyridge/northbridge.c

@@ -340,7 +340,7 @@ void amd_initcpuio(void)
 
 	/* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */
 	base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;
-	limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP;
+	limit = (ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8) | MMIO_NP;
 	pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit);
 	pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base);