drivers/amd/agesa/cache_as_ram.S: Fix coding style
Change-Id: Iada9b3ba71b991b6f9c7ebb5f300c8d28829ab4f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Elyes HAOUAS
Kyösti Mälkki
parent
2cc351da5f
commit
dea45c1060
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@ -33,86 +33,86 @@
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_cache_as_ram_setup:
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/* Preserve BIST. */
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movd %eax, %mm0
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/* Preserve BIST. */
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movd %eax, %mm0
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post_code(0xa0)
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post_code(0xa0)
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/* enable SSE2 128bit instructions */
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/* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
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/* enable SSE2 128bit instructions */
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/* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
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movl %cr4, %eax
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orl $(3 << 9), %eax
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movl %eax, %cr4
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movl %cr4, %eax
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orl $(3 << 9), %eax
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movl %eax, %cr4
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post_code(0xa1)
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post_code(0xa1)
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AMD_ENABLE_STACK
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AMD_ENABLE_STACK
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/* Align the stack. */
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and $0xFFFFFFF0, %esp
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/* Align the stack. */
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and $0xFFFFFFF0, %esp
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#ifdef __x86_64__
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/* switch to 64 bit long mode */
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mov %esi, %ecx
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add $0, %ecx # core number
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xor %eax, %eax
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lea (0x1000+0x23)(%ecx), %edi
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mov %edi, (%ecx)
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mov %eax, 4(%ecx)
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/* switch to 64 bit long mode */
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mov %esi, %ecx
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add $0, %ecx # core number
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xor %eax, %eax
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lea (0x1000+0x23)(%ecx), %edi
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mov %edi, (%ecx)
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mov %eax, 4(%ecx)
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lea 0x1000(%ecx), %edi
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movl $0x000000e3, 0x00(%edi)
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movl %eax, 0x04(%edi)
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movl $0x400000e3, 0x08(%edi)
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movl %eax, 0x0c(%edi)
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movl $0x800000e3, 0x10(%edi)
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movl %eax, 0x14(%edi)
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movl $0xc00000e3, 0x18(%edi)
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movl %eax, 0x1c(%edi)
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lea 0x1000(%ecx), %edi
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movl $0x000000e3, 0x00(%edi)
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movl %eax, 0x04(%edi)
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movl $0x400000e3, 0x08(%edi)
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movl %eax, 0x0c(%edi)
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movl $0x800000e3, 0x10(%edi)
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movl %eax, 0x14(%edi)
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movl $0xc00000e3, 0x18(%edi)
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movl %eax, 0x1c(%edi)
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# load ROM based identity mapped page tables
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mov %ecx, %eax
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mov %eax, %cr3
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# load ROM based identity mapped page tables
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mov %ecx, %eax
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mov %eax, %cr3
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# enable PAE
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mov %cr4, %eax
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bts $5, %eax
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mov %eax, %cr4
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# enable PAE
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mov %cr4, %eax
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bts $5, %eax
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mov %eax, %cr4
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# enable long mode
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mov $0xC0000080, %ecx
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rdmsr
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bts $8, %eax
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wrmsr
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# enable long mode
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mov $0xC0000080, %ecx
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rdmsr
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bts $8, %eax
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wrmsr
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# enable paging
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mov %cr0, %eax
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bts $31, %eax
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mov %eax, %cr0
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# enable paging
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mov %cr0, %eax
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bts $31, %eax
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mov %eax, %cr0
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# use call far to switch to 64-bit code segment
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ljmp $0x18, $1f
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# use call far to switch to 64-bit code segment
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ljmp $0x18, $1f
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1:
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#endif
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call early_all_cores
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call early_all_cores
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/* Must maintain 16-byte stack alignment here. */
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pushl $0x0
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pushl $0x0
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pushl $0x0
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movd %mm0, %eax /* bist */
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pushl %eax
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call romstage_main
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/* Must maintain 16-byte stack alignment here. */
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pushl $0x0
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pushl $0x0
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pushl $0x0
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movd %mm0, %eax /* bist */
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pushl %eax
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call romstage_main
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#if IS_ENABLED(CONFIG_POSTCAR_STAGE)
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/* We do not return. Execution continues with run_postcar_phase()
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* calling to chipset_teardown_car below.
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*/
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jmp postcar_entry_failure
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jmp postcar_entry_failure
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chipset_teardown_car:
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@ -120,53 +120,53 @@ chipset_teardown_car:
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* Retrieve return address from stack as it will get trashed below if
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* execution is utilizing the cache-as-ram stack.
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*/
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pop %esp
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pop %esp
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#else
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movl %eax, %esp
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movl %eax, %esp
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/* Register %esp is new stacktop for remaining of romstage. */
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#endif
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/* Disable cache */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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/* Disable cache */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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/* Register %esp is preserved in AMD_DISABLE_STACK. */
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AMD_DISABLE_STACK
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AMD_DISABLE_STACK
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#if IS_ENABLED(CONFIG_POSTCAR_STAGE)
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jmp *%esp
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jmp *%esp
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#else
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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call romstage_after_car
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call romstage_after_car
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#endif
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/* Should never see this postcode */
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post_code(0xaf)
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/* Should never see this postcode */
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post_code(0xaf)
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stop:
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hlt
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jmp stop
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hlt
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jmp stop
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/* These are here for linking purposes. */
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.weak early_all_cores, romstage_main
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early_all_cores:
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romstage_main:
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postcar_entry_failure:
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/* Should never see this postcode */
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post_code(0xae)
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jmp stop
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/* Should never see this postcode */
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post_code(0xae)
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jmp stop
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_cache_as_ram_setup_end:
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