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drivers/amd/agesa/cache_as_ram.S: Fix coding style

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Change-Id: Iada9b3ba71b991b6f9c7ebb5f300c8d28829ab4f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Elyes HAOUAS 2018-12-27 09:14:07 +01:00 committed by Kyösti Mälkki
parent 2cc351da5f
commit dea45c1060
1 changed files with 75 additions and 75 deletions
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150
src/drivers/amd/agesa/cache_as_ram.S
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@ -33,86 +33,86 @@
_cache_as_ram_setup: _cache_as_ram_setup:
/* Preserve BIST. */ /* Preserve BIST. */
movd %eax, %mm0 movd %eax, %mm0
post_code(0xa0) post_code(0xa0)
/* enable SSE2 128bit instructions */ /* enable SSE2 128bit instructions */
/* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
movl %cr4, %eax movl %cr4, %eax
orl $(3 << 9), %eax orl $(3 << 9), %eax
movl %eax, %cr4 movl %eax, %cr4
post_code(0xa1) post_code(0xa1)
AMD_ENABLE_STACK AMD_ENABLE_STACK
/* Align the stack. */ /* Align the stack. */
and $0xFFFFFFF0, %esp and $0xFFFFFFF0, %esp
#ifdef __x86_64__ #ifdef __x86_64__
/* switch to 64 bit long mode */ /* switch to 64 bit long mode */
mov %esi, %ecx mov %esi, %ecx
add $0, %ecx # core number add $0, %ecx # core number
xor %eax, %eax xor %eax, %eax
lea (0x1000+0x23)(%ecx), %edi lea (0x1000+0x23)(%ecx), %edi
mov %edi, (%ecx) mov %edi, (%ecx)
mov %eax, 4(%ecx) mov %eax, 4(%ecx)
lea 0x1000(%ecx), %edi lea 0x1000(%ecx), %edi
movl $0x000000e3, 0x00(%edi) movl $0x000000e3, 0x00(%edi)
movl %eax, 0x04(%edi) movl %eax, 0x04(%edi)
movl $0x400000e3, 0x08(%edi) movl $0x400000e3, 0x08(%edi)
movl %eax, 0x0c(%edi) movl %eax, 0x0c(%edi)
movl $0x800000e3, 0x10(%edi) movl $0x800000e3, 0x10(%edi)
movl %eax, 0x14(%edi) movl %eax, 0x14(%edi)
movl $0xc00000e3, 0x18(%edi) movl $0xc00000e3, 0x18(%edi)
movl %eax, 0x1c(%edi) movl %eax, 0x1c(%edi)
# load ROM based identity mapped page tables # load ROM based identity mapped page tables
mov %ecx, %eax mov %ecx, %eax
mov %eax, %cr3 mov %eax, %cr3
# enable PAE # enable PAE
mov %cr4, %eax mov %cr4, %eax
bts $5, %eax bts $5, %eax
mov %eax, %cr4 mov %eax, %cr4
# enable long mode # enable long mode
mov $0xC0000080, %ecx mov $0xC0000080, %ecx
rdmsr rdmsr
bts $8, %eax bts $8, %eax
wrmsr wrmsr
# enable paging # enable paging
mov %cr0, %eax mov %cr0, %eax
bts $31, %eax bts $31, %eax
mov %eax, %cr0 mov %eax, %cr0
# use call far to switch to 64-bit code segment # use call far to switch to 64-bit code segment
ljmp $0x18, $1f ljmp $0x18, $1f
1: 1:
#endif #endif
call early_all_cores call early_all_cores
/* Must maintain 16-byte stack alignment here. */ /* Must maintain 16-byte stack alignment here. */
pushl $0x0 pushl $0x0
pushl $0x0 pushl $0x0
pushl $0x0 pushl $0x0
movd %mm0, %eax /* bist */ movd %mm0, %eax /* bist */
pushl %eax pushl %eax
call romstage_main call romstage_main
#if IS_ENABLED(CONFIG_POSTCAR_STAGE) #if IS_ENABLED(CONFIG_POSTCAR_STAGE)
/* We do not return. Execution continues with run_postcar_phase() /* We do not return. Execution continues with run_postcar_phase()
* calling to chipset_teardown_car below. * calling to chipset_teardown_car below.
*/ */
jmp postcar_entry_failure jmp postcar_entry_failure
chipset_teardown_car: chipset_teardown_car:
@ -120,53 +120,53 @@ chipset_teardown_car:
* Retrieve return address from stack as it will get trashed below if * Retrieve return address from stack as it will get trashed below if
* execution is utilizing the cache-as-ram stack. * execution is utilizing the cache-as-ram stack.
*/ */
pop %esp pop %esp
#else #else
movl %eax, %esp movl %eax, %esp
/* Register %esp is new stacktop for remaining of romstage. */ /* Register %esp is new stacktop for remaining of romstage. */
#endif #endif
/* Disable cache */ /* Disable cache */
movl %cr0, %eax movl %cr0, %eax
orl $CR0_CacheDisable, %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
/* Register %esp is preserved in AMD_DISABLE_STACK. */ /* Register %esp is preserved in AMD_DISABLE_STACK. */
AMD_DISABLE_STACK AMD_DISABLE_STACK
#if IS_ENABLED(CONFIG_POSTCAR_STAGE) #if IS_ENABLED(CONFIG_POSTCAR_STAGE)
jmp *%esp jmp *%esp
#else #else
/* enable cache */ /* enable cache */
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff, %eax andl $0x9fffffff, %eax
movl %eax, %cr0 movl %eax, %cr0
call romstage_after_car call romstage_after_car
#endif #endif
/* Should never see this postcode */ /* Should never see this postcode */
post_code(0xaf) post_code(0xaf)
stop: stop:
hlt hlt
jmp stop jmp stop
/* These are here for linking purposes. */ /* These are here for linking purposes. */
.weak early_all_cores, romstage_main .weak early_all_cores, romstage_main
early_all_cores: early_all_cores:
romstage_main: romstage_main:
postcar_entry_failure: postcar_entry_failure:
/* Should never see this postcode */ /* Should never see this postcode */
post_code(0xae) post_code(0xae)
jmp stop jmp stop
_cache_as_ram_setup_end: _cache_as_ram_setup_end: