lynxpoint: Fix up handling for LynxPoint-LP chipsets
This configures power management registers according to the 1.2.0 reference code drop. There are many inconsistencies with the documentation and I tried to note those with ?. This does not do the same for LynxPoint-H yet. Change-Id: I9b8f5c24a8b0931075a44398571c9b0d54cce6a6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2819 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Duncan Laurie
Ronald G. Minnich
parent
70f04b41ce
commit
deb90f4759
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@ -307,49 +307,96 @@ static void pch_rtc_init(struct device *dev)
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rtc_init(rtc_failed);
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}
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/* CougarPoint PCH Power Management init */
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#if 0
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static void cpt_pm_init(struct device *dev)
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/* LynxPoint PCH Power Management init */
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static void lpt_pm_init(struct device *dev)
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{
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printk(BIOS_DEBUG, "CougarPoint PM init\n");
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pci_write_config8(dev, 0xa9, 0x47);
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RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0));
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RCBA32_AND_OR(0x228c, ~0UL, (1 << 0));
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RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14));
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RCBA16_AND_OR(0x0900, ~0UL, (1 << 14));
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RCBA32(0x2304) = 0xc0388400;
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RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18));
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RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1));
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RCBA32_AND_OR(0x3314, ~0x1f, 0xf);
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RCBA32(0x3318) = 0x050f0000;
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RCBA32(0x3324) = 0x04000000;
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RCBA32_AND_OR(0x3340, ~0UL, 0xfffff);
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RCBA32_AND_OR(0x3344, ~0UL, (1 << 1));
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RCBA32(0x3360) = 0x0001c000;
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RCBA32(0x3368) = 0x00061100;
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RCBA32(0x3378) = 0x7f8fdfff;
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RCBA32(0x337c) = 0x000003fc;
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RCBA32(0x3388) = 0x00001000;
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RCBA32(0x3390) = 0x0001c000;
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RCBA32(0x33a0) = 0x00000800;
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RCBA32(0x33b0) = 0x00001000;
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RCBA32(0x33c0) = 0x00093900;
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RCBA32(0x33cc) = 0x24653002;
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RCBA32(0x33d0) = 0x062108fe;
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RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060);
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RCBA32(0x3a28) = 0x01010000;
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RCBA32(0x3a2c) = 0x01010404;
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RCBA32(0x3a80) = 0x01041041;
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RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001);
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RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
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RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */
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RCBA32(0x3a6c) = 0x00000001;
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RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c);
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RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20);
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RCBA32(0x33c8) = 0;
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RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
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printk(BIOS_DEBUG, "LynxPoint PM init\n");
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}
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const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
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RCBA_RMW_REG_32(0x232c, ~1, 0x00000000), /* 4 */
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RCBA_RMW_REG_32(0x1100, ~0, 0x0000c000), /* 5 */
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RCBA_RMW_REG_32(0x1100, ~0, 0x00000100), /* 6 */
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RCBA_RMW_REG_32(0x1100, ~0, 0x0000003f), /* 7 */
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RCBA_RMW_REG_32(0x2320, ~0x60, 0x10), /* 8? */
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RCBA_RMW_REG_32(0x3314, 0, 0x00012fff), /* 9? */
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RCBA_RMW_REG_32(0x3318, 0, 0x0dcf0400), /* 10? */
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RCBA_RMW_REG_32(0x3324, 0, 0x04000000), /* 11 */
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RCBA_RMW_REG_32(0x3368, 0, 0x00041400), /* 12? */
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RCBA_RMW_REG_32(0x3388, 0, 0x3f8ddbff), /* 13? */
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RCBA_RMW_REG_32(0x33ac, 0, 0x00007001), /* 14? */
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RCBA_RMW_REG_32(0x33b0, 0, 0x00181900), /* 15? */
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RCBA_RMW_REG_32(0x33c0, 0, 0x00060A00), /* 16? */
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RCBA_RMW_REG_32(0x33d0, 0, 0x06200840), /* 17? */
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RCBA_RMW_REG_32(0x3a28, 0, 0x01010101), /* 19 */
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RCBA_RMW_REG_32(0x3a2c, 0, 0x04040404), /* 20 */
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RCBA_RMW_REG_32(0x2b1c, 0, 0x03808033), /* 23? */
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RCBA_RMW_REG_32(0x2b34, 0, 0x80000008), /* 24 */
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RCBA_RMW_REG_32(0x3348, 0, 0x022ddfff), /* 25? */
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RCBA_RMW_REG_32(0x334c, 0, 0x00000001), /* 26 */
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RCBA_RMW_REG_32(0x3358, 0, 0x0001c000), /* 27 */
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RCBA_RMW_REG_32(0x3380, 0, 0x3f8ddbff), /* 28 */
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RCBA_RMW_REG_32(0x3384, 0, 0x0001c7e1), /* 29 */
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RCBA_RMW_REG_32(0x338c, 0, 0x0001c7e1), /* ? */
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RCBA_RMW_REG_32(0x3398, 0, 0x0001c000), /* 30 */
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RCBA_RMW_REG_32(0x33a8, 0, 0x00181900), /* 31? */
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RCBA_RMW_REG_32(0x33dc, 0, 0x00080000), /* 32 */
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RCBA_RMW_REG_32(0x33e0, 0, 0x00000001), /* 33 */
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RCBA_RMW_REG_32(0x3a20, 0, 0x00000404), /* 34 */
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RCBA_RMW_REG_32(0x3a24, 0, 0x01010101), /* 35 */
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RCBA_RMW_REG_32(0x3a30, 0, 0x01010101), /* 36 */
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RCBA_RMW_REG_32(0x0410, ~0, 0x00000003), /* 42 */
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RCBA_RMW_REG_32(0x2618, ~0, 0x08000000), /* 43 */
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RCBA_RMW_REG_32(0x2600, ~0, 0x00000008), /* 44 */
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RCBA_RMW_REG_32(0x33b4, 0, 0x00007001), /* 46? */
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RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff), /* 47? */
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RCBA_RMW_REG_32(0x3354, 0, 0x00000001), /* ? */
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RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */
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RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080), /* Power Optimizer */
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RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */
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RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4610), /* Power Optimizer */
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RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */
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RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */
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RCBA_RMW_REG_32(0x3a80, 0, 0x05145005), /* 21? */
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RCBA_END_CONFIG
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};
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/* LynxPoint LP PCH Power Management init */
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static void lpt_lp_pm_init(struct device *dev)
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{
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struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
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u32 data;
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printk(BIOS_DEBUG, "LynxPoint LP PM init\n");
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pci_write_config8(dev, 0xa9, 0x46);
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pch_config_rcba(lpt_lp_pm_rcba);
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pci_write_config32(dev, 0xac,
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pci_read_config32(dev, 0xac) | (1 << 21));
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pch_iobp_update(0xCA000000, ~0UL, 0x00000009);
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/* Set RCBA CIR28 0x3A84 based on SATA port enables */
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data = 0x00001005;
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/* Port 3 and 2 disabled */
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if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0)
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data |= (1 << 24) | (1 << 26);
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/* Port 1 and 0 disabled */
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if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0)
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data |= (1 << 20) | (1 << 18);
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RCBA32(0x3a84) = data;
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/* Lock */
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RCBA32_OR(0x3a6c, 0x00000001);
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/* Set RCBA 0x33D4 after other setup */
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RCBA32_OR(0x33d4, 0x2fff2fb1);
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/* Set RCBA 0x33C8[15]=1 as last step */
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RCBA32_OR(0x33c8, (1 << 15));
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}
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#endif
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static void enable_hpet(void)
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{
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@ -366,45 +413,6 @@ static void enable_hpet(void)
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static void enable_clock_gating(device_t dev)
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{
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#if CONFIG_INTEL_LYNXPOINT_LP
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/* LynxPoint LP */
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u32 reg32;
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u16 reg16;
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/* DMI */
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RCBA32_AND_OR(0x2234, ~0UL, 0xf);
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reg16 = pci_read_config16(dev, GEN_PMCON_1);
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reg16 &= ~((1 << 11) | (1 << 14));
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reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13);
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reg16 |= (1 << 2); // PCI CLKRUN# Enable
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pci_write_config16(dev, GEN_PMCON_1, reg16);
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reg32 = pci_read_config32(dev, 0x64);
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reg32 |= (1 << 6);
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pci_write_config32(dev, 0x64, reg32);
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RCBA32_AND_OR(0x2614, 0x8fffffff, 0x0f006500);
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RCBA32_OR(0x900, 0x0000031f);
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reg32 = RCBA32(CG);
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reg32 |= (1 << 31); // LPC Dynamic
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reg32 |= (1 << 30); // LP LPC
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reg32 |= (1 << 28); // GPIO Dynamic
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reg32 |= (1 << 27); // HPET Dynamic
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reg32 |= (1 << 26); // LP LPC
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reg32 |= (1 << 22); // HDA Dynamic
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reg32 |= (1 << 16); // PCIe Dynamic
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RCBA32(CG) = reg32;
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RCBA32_OR(0x3434, 0x7); // LP LPC
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RCBA32_AND_OR(0x333c, 0xff0fffff, 0x00800000); // SATA
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RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic
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pch_iobp_update(0xCF000000, ~0UL, 0x00007001);
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pch_iobp_update(0xCE00C000, ~0UL, 0x00000001);
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#else
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/* LynxPoint Mobile */
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u32 reg32;
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u16 reg16;
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@ -426,7 +434,47 @@ static void enable_clock_gating(device_t dev)
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RCBA32(CG) = reg32;
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RCBA32_OR(0x38c0, 0x7); // SPI Dynamic
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#endif
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}
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static void enable_lp_clock_gating(device_t dev)
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{
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/* LynxPoint LP */
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u32 reg32;
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u16 reg16;
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/* DMI */
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RCBA32_AND_OR(0x2234, ~0UL, 0xf);
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reg16 = pci_read_config16(dev, GEN_PMCON_1);
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reg16 &= ~((1 << 11) | (1 << 14));
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reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13);
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reg16 |= (1 << 2); // PCI CLKRUN# Enable
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pci_write_config16(dev, GEN_PMCON_1, reg16);
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reg32 = pci_read_config32(dev, 0x64);
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reg32 |= (1 << 6);
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pci_write_config32(dev, 0x64, reg32);
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RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500);
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RCBA32_OR(0x900, 0x0000031f);
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reg32 = RCBA32(CG);
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reg32 |= (1 << 31); // LPC Dynamic
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reg32 |= (1 << 30); // LP LPC
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reg32 |= (1 << 28); // GPIO Dynamic
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reg32 |= (1 << 27); // HPET Dynamic
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reg32 |= (1 << 26); // LP LPC
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reg32 |= (1 << 22); // HDA Dynamic
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reg32 |= (1 << 16); // PCIe Dynamic
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RCBA32(CG) = reg32;
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RCBA32_OR(0x3434, 0x7); // LP LPC
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RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA
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RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic
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pch_iobp_update(0xCF000000, ~0UL, 0x00007001);
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pch_iobp_update(0xCE00C000, ~0UL, 0x00000001);
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}
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static void pch_set_acpi_mode(void)
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@ -504,14 +552,14 @@ static void lpc_init(struct device *dev)
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pch_power_options(dev);
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/* Initialize power management */
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switch (pch_silicon_type()) {
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default:
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printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device);
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if (pch_is_lp()) {
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lpt_lp_pm_init(dev);
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enable_lp_clock_gating(dev);
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} else {
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lpt_pm_init(dev);
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enable_clock_gating(dev);
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}
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/* Set the state of the GPIO lines. */
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//gpio_init(dev);
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/* Initialize the real time clock. */
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pch_rtc_init(dev);
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@ -521,12 +569,8 @@ static void lpc_init(struct device *dev)
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/* Initialize the High Precision Event Timers, if present. */
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enable_hpet();
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/* Initialize Clock Gating */
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enable_clock_gating(dev);
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setup_i8259();
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/* The OS should do this? */
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/* Interrupt 9 should be level triggered (SCI) */
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i8259_configure_irq_trigger(9, 1);
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