vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1514_11
List of changes: FSP-S Header: - Add UPD MicrocodeRegionBase and MicrocodeRegionSize - Adjust UPD Offset for Reservedxx Change-Id: I376abf6cd64dcf8c848901074e2c2f30d4f302da Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This commit is contained in:
Subrata Banik
parent
a69d682a0b
commit
deba7deda6
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@ -102,7 +102,21 @@ typedef struct {
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/** Offset 0x0055 - Reserved
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**/
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UINT8 Reserved1[12];
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UINT8 Reserved1[3];
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/** Offset 0x0058 - MicrocodeRegionBase
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Memory Base of Microcode Updates
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**/
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UINT32 MicrocodeRegionBase;
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/** Offset 0x005C - MicrocodeRegionSize
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Size of Microcode Updates
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**/
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UINT32 MicrocodeRegionSize;
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/** Offset 0x0060 - Reserved
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**/
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UINT8 Reserved2;
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/** Offset 0x0061 - Enable SATA SALP Support
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Enable/disable SATA Aggressive Link Power Management.
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@ -124,7 +138,7 @@ typedef struct {
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/** Offset 0x0072 - Reserved
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**/
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UINT8 Reserved2[34];
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UINT8 Reserved3[34];
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/** Offset 0x0094 - Enable USB2 ports
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Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
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@ -146,7 +160,7 @@ typedef struct {
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/** Offset 0x00AF - Reserved
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**/
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UINT8 Reserved3[26];
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UINT8 Reserved4[26];
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/** Offset 0x00C9 - Enable SATA
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Enable/disable SATA controller.
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@ -168,7 +182,7 @@ typedef struct {
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/** Offset 0x00D2 - Reserved
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**/
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UINT8 Reserved4[35];
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UINT8 Reserved5[35];
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/** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW
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Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
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@ -191,7 +205,7 @@ typedef struct {
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/** Offset 0x010A - Reserved
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**/
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UINT8 Reserved5[65];
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UINT8 Reserved6[65];
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/** Offset 0x014B - Enables UART hardware flow control, CTS and RTS lines
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Enables UART hardware flow control, CTS and RTS lines.
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@ -200,7 +214,7 @@ typedef struct {
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/** Offset 0x0152 - Reserved
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**/
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UINT8 Reserved6[2];
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UINT8 Reserved7[2];
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/** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy
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Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
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@ -236,7 +250,7 @@ typedef struct {
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/** Offset 0x01C5 - Reserved
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**/
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UINT8 Reserved7[7];
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UINT8 Reserved8[7];
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/** Offset 0x01CC - I2Cn Device Mode
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Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
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@ -258,7 +272,7 @@ typedef struct {
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/** Offset 0x0214 - Reserved
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**/
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UINT8 Reserved8[192];
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UINT8 Reserved9[192];
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/** Offset 0x02D4 - USB Per Port HS Preemphasis Bias
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USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
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@ -310,7 +324,7 @@ typedef struct {
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/** Offset 0x033C - Reserved
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**/
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UINT8 Reserved9[80];
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UINT8 Reserved10[80];
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/** Offset 0x038C - Enable LAN
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Enable/disable LAN controller.
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@ -320,7 +334,7 @@ typedef struct {
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/** Offset 0x038D - Reserved
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**/
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UINT8 Reserved10[11];
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UINT8 Reserved11[11];
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/** Offset 0x0398 - PCIe PTM enable/disable
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Enable/disable Precision Time Measurement for PCIE Root Ports.
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@ -329,7 +343,7 @@ typedef struct {
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/** Offset 0x03B4 - Reserved
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**/
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UINT8 Reserved11[81];
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UINT8 Reserved12[81];
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/** Offset 0x0405 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
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This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
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@ -345,7 +359,7 @@ typedef struct {
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/** Offset 0x0407 - Reserved
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**/
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UINT8 Reserved12;
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UINT8 Reserved13;
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/** Offset 0x0408 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
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This field has 1us resolution. When value is 0 Transition to 0V is disabled.
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@ -354,7 +368,7 @@ typedef struct {
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/** Offset 0x040A - Reserved
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**/
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UINT8 Reserved13[50];
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UINT8 Reserved14[50];
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/** Offset 0x043C - CNVi Configuration
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This option allows for automatic detection of Connectivity Solution. [Auto Detection]
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@ -377,7 +391,7 @@ typedef struct {
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/** Offset 0x043F - Reserved
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**/
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UINT8 Reserved14;
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UINT8 Reserved15;
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/** Offset 0x0440 - CNVi RF_RESET pin muxing
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Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default)
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@ -394,7 +408,7 @@ typedef struct {
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/** Offset 0x0448 - Reserved
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**/
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UINT8 Reserved15[172];
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UINT8 Reserved16[172];
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/** Offset 0x04F4 - CdClock Frequency selection
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0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2:
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@ -419,7 +433,7 @@ typedef struct {
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/** Offset 0x04F7 - Reserved
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**/
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UINT8 Reserved16;
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UINT8 Reserved17;
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/** Offset 0x04F8 - TypeC port GPIO setting
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GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
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@ -430,7 +444,7 @@ typedef struct {
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/** Offset 0x0518 - Reserved
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**/
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UINT8 Reserved17[8];
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UINT8 Reserved18[8];
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/** Offset 0x0520 - Enable D3 Cold in TCSS
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This policy will enable/disable D3 cold support in IOM
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@ -440,7 +454,7 @@ typedef struct {
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/** Offset 0x0521 - Reserved
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**/
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UINT8 Reserved18[8];
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UINT8 Reserved19[8];
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/** Offset 0x0529 - Enable VMD controller
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Enable/disable to VMD controller.0: Disable(Default); 1: Enable
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@ -450,7 +464,7 @@ typedef struct {
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/** Offset 0x052A - Reserved
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**/
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UINT8 Reserved19[120];
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UINT8 Reserved20[120];
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/** Offset 0x05A2 - TCSS Aux Orientation Override Enable
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Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
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@ -464,7 +478,7 @@ typedef struct {
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/** Offset 0x05A6 - Reserved
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**/
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UINT8 Reserved20;
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UINT8 Reserved21;
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/** Offset 0x05A7 - ITBT Root Port Enable
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ITBT Root Port Enable, 0:Disable, 1:Enable
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@ -474,7 +488,7 @@ typedef struct {
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/** Offset 0x05AB - Reserved
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**/
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UINT8 Reserved21[3];
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UINT8 Reserved22[3];
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/** Offset 0x05AE - ITbtConnectTopology Timeout value
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ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
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@ -484,7 +498,7 @@ typedef struct {
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/** Offset 0x05B0 - Reserved
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**/
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UINT8 Reserved22[7];
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UINT8 Reserved23[7];
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/** Offset 0x05B7 - Enable/Disable PTM
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This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
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@ -494,7 +508,7 @@ typedef struct {
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/** Offset 0x05BB - Reserved
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**/
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UINT8 Reserved23[200];
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UINT8 Reserved24[200];
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/** Offset 0x0683 - Skip Multi-Processor Initialization
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When this is skipped, boot loader must initialize processors before SilicionInit
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@ -505,7 +519,7 @@ typedef struct {
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/** Offset 0x0684 - Reserved
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**/
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UINT8 Reserved24[8];
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UINT8 Reserved25[8];
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/** Offset 0x068C - CpuMpPpi
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<b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
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@ -516,7 +530,7 @@ typedef struct {
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/** Offset 0x0690 - Reserved
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**/
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UINT8 Reserved25[74];
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UINT8 Reserved26[74];
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/** Offset 0x06DA - Enable Power Optimizer
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Enable DMI Power Optimizer on PCH side.
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@ -526,7 +540,7 @@ typedef struct {
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/** Offset 0x06DB - Reserved
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**/
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UINT8 Reserved26[33];
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UINT8 Reserved27[33];
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/** Offset 0x06FC - Enable PCH ISH SPI Cs0 pins assigned
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Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
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@ -535,7 +549,7 @@ typedef struct {
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/** Offset 0x06FD - Reserved
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**/
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UINT8 Reserved27[2];
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UINT8 Reserved28[2];
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/** Offset 0x06FF - Enable PCH ISH SPI pins assigned
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Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
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@ -559,7 +573,7 @@ typedef struct {
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/** Offset 0x070D - Reserved
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**/
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UINT8 Reserved28[2];
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UINT8 Reserved29[2];
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/** Offset 0x070F - Enable LOCKDOWN BIOS LOCK
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Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
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@ -570,7 +584,7 @@ typedef struct {
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/** Offset 0x0710 - Reserved
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**/
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UINT8 Reserved29[2];
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UINT8 Reserved30[2];
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/** Offset 0x0712 - RTC Cmos Memory Lock
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Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
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@ -586,7 +600,7 @@ typedef struct {
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/** Offset 0x072F - Reserved
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**/
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UINT8 Reserved30[56];
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UINT8 Reserved31[56];
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/** Offset 0x0767 - Enable PCIE RP Clk Req Detect
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Probe CLKREQ# signal before enabling CLKREQ# based power management.
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@ -600,7 +614,7 @@ typedef struct {
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/** Offset 0x079F - Reserved
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**/
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UINT8 Reserved31[196];
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UINT8 Reserved32[196];
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/** Offset 0x0863 - PCIE RP Max Payload
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Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
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@ -615,7 +629,7 @@ typedef struct {
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/** Offset 0x0880 - Reserved
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**/
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UINT8 Reserved32[5];
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UINT8 Reserved33[5];
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/** Offset 0x0885 - Touch Host Controller Port 1 Assignment
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Assign THC Port 1
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@ -625,7 +639,7 @@ typedef struct {
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/** Offset 0x0886 - Reserved
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**/
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UINT8 Reserved33[91];
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UINT8 Reserved34[91];
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/** Offset 0x08E1 - PCIE RP Aspm
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The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
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@ -641,7 +655,7 @@ typedef struct {
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/** Offset 0x0919 - Reserved
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**/
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UINT8 Reserved34[28];
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UINT8 Reserved35[28];
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/** Offset 0x0935 - PCIE RP Ltr Enable
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Latency Tolerance Reporting Mechanism.
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@ -650,7 +664,7 @@ typedef struct {
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/** Offset 0x0951 - Reserved
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**/
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UINT8 Reserved35[132];
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UINT8 Reserved36[132];
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/** Offset 0x09D5 - PCH Sata Pwr Opt Enable
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SATA Power Optimizer on PCH side.
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@ -660,7 +674,7 @@ typedef struct {
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/** Offset 0x09D6 - Reserved
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**/
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UINT8 Reserved36[50];
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UINT8 Reserved37[50];
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/** Offset 0x0A08 - Enable SATA Port DmVal
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DITO multiplier. Default is 15.
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@ -674,7 +688,7 @@ typedef struct {
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/** Offset 0x0A20 - Reserved
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**/
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UINT8 Reserved37[62];
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UINT8 Reserved38[62];
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/** Offset 0x0A5E - USB2 Port Over Current Pin
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Describe the specific over current pin number of USB 2.0 Port N.
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@ -688,7 +702,7 @@ typedef struct {
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/** Offset 0x0A78 - Reserved
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**/
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UINT8 Reserved38[16];
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UINT8 Reserved39[16];
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/** Offset 0x0A88 - Enable 8254 Static Clock Gating
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Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
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@ -708,7 +722,7 @@ typedef struct {
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/** Offset 0x0A8A - Reserved
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**/
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UINT8 Reserved39;
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UINT8 Reserved40;
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/** Offset 0x0A8B - Hybrid Storage Detection and Configuration Mode
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Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
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@ -719,7 +733,7 @@ typedef struct {
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/** Offset 0x0A8C - Reserved
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**/
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UINT8 Reserved40[93];
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UINT8 Reserved41[93];
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/** Offset 0x0AE9 - Enable PS_ON.
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PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
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@ -731,7 +745,7 @@ typedef struct {
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/** Offset 0x0AEA - Reserved
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**/
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UINT8 Reserved41[318];
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UINT8 Reserved42[318];
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/** Offset 0x0C28 - RpPtmBytes
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**/
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@ -739,7 +753,7 @@ typedef struct {
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/** Offset 0x0C2C - Reserved
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**/
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UINT8 Reserved42[95];
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UINT8 Reserved43[95];
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/** Offset 0x0C8B - Enable/Disable IGFX PmSupport
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Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
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@ -749,7 +763,7 @@ typedef struct {
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/** Offset 0x0C8C - Reserved
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**/
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UINT8 Reserved43;
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UINT8 Reserved44;
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/** Offset 0x0C8D - GT Frequency Limit
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0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
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@ -767,7 +781,7 @@ typedef struct {
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/** Offset 0x0C8E - Reserved
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**/
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UINT8 Reserved44[24];
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UINT8 Reserved45[24];
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/** Offset 0x0CA6 - Enable or Disable HWP
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Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
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@ -778,7 +792,7 @@ typedef struct {
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/** Offset 0x0CA7 - Reserved
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**/
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UINT8 Reserved45[8];
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UINT8 Reserved46[8];
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/** Offset 0x0CAF - TCC Activation Offset
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TCC Activation Offset. Offset from factory set TCC activation temperature at which
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@ -790,7 +804,7 @@ typedef struct {
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/** Offset 0x0CB0 - Reserved
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**/
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UINT8 Reserved46[34];
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UINT8 Reserved47[34];
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/** Offset 0x0CD2 - Enable or Disable CPU power states (C-states)
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Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
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@ -800,7 +814,7 @@ typedef struct {
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/** Offset 0x0CD3 - Reserved
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**/
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UINT8 Reserved47[196];
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UINT8 Reserved48[196];
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/** Offset 0x0D97 - Enable LOCKDOWN SMI
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Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
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@ -822,7 +836,7 @@ typedef struct {
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/** Offset 0x0D9A - Reserved
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**/
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UINT8 Reserved48[2];
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UINT8 Reserved49[2];
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/** Offset 0x0D9C - PCIE RP Ltr Max Snoop Latency
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Latency Tolerance Reporting, Max Snoop Latency.
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@ -836,7 +850,7 @@ typedef struct {
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/** Offset 0x0E0C - Reserved
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**/
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UINT8 Reserved49[313];
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UINT8 Reserved50[313];
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/** Offset 0x0F45 - LpmStateEnableMask
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**/
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@ -844,7 +858,7 @@ typedef struct {
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/** Offset 0x0F46 - Reserved
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**/
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UINT8 Reserved50[698];
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UINT8 Reserved51[698];
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} FSP_S_CONFIG;
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/** Fsp S UPD Configuration
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