vc/intel/fsp: Update ADL N FSP headers from v3222.03 to v3267.01

Update generated FSP headers for Alder Lake N from v3222.03 to v3267.01.

Changes include:
- Add UPD Lp5BankMode
- Update UPD Offset in FspmUpd.h

BUG=b:240373012
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa.

Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb522e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66222
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h

@@ -3201,7 +3201,17 @@ typedef struct {
 
 /** Offset 0x0AA8 - Reserved
 **/
-  UINT8                       Reserved45[144];
+  UINT8                       Reserved45[130];
+
+/** Offset 0x0B2A -  LP5 Bank Mode
+  LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0
+  0:Auto, 1:8 Bank Mode, 2:16 Bank Mode, 3:BG Mode
+**/
+  UINT8                       Lp5BankMode;
+
+/** Offset 0x0B2B - Reserved
+**/
+  UINT8                       Reserved46[13];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
@@ -3222,7 +3232,7 @@ typedef struct {
 
 /** Offset 0x0B38
 **/
-  UINT8                       UnusedUpdSpace34[6];
+  UINT8                       UnusedUpdSpace33[6];
 
 /** Offset 0x0B3E
 **/