diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
index 30e5e454dc..7496428cf7 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -2,9 +2,6 @@ chip soc/intel/jasperlake
 	# MIPI display panel
 	register "DdiPortAConfig" = "2" # DdiPortMipiDsi
 
-	# Core Display Clock Frequency selection
-	register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
 	# Enable Acoustic noise mitigation and set slew rate to 1/8
 	# Rest of the parameters are 0 by default.
 	register "AcousticNoiseMitigation" = "1"
diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
index 73a5f49a37..fcf66f2bdb 100644
--- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
@@ -75,9 +75,6 @@ chip soc/intel/jasperlake
 
 	register "tcc_offset" = "8"     # TCC of 97C
 
-	# Core Display Clock Frequency selection
-	register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
 	device domain 0 on
 		device pci 04.0 on
 			# Default DPTF Policy for all Dedede boards if not overridden
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index e0af22dd49..66fc4ea02f 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -108,9 +108,6 @@ chip soc/intel/jasperlake
 	register "SlowSlewRate" = "SlewRateFastBy8"
 	register "FastPkgCRampDisable" = "1"
 
-	# Core Display Clock Frequency selection
-	register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
 	device domain 0 on
 		device pci 04.0 on
 			chip drivers/intel/dptf
diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
index 06da2d48c3..bb4762f82c 100644
--- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
@@ -69,9 +69,6 @@ chip soc/intel/jasperlake
 		.tdp_pl2_override = 12,
 	}"
 
-	# Core Display Clock Frequency selection
-	register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
 	device domain 0 on
 		device pci 04.0 on
 			chip drivers/intel/dptf
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 398fe71699..896a79a0f9 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -417,8 +417,6 @@ struct soc_intel_jasperlake_config {
 		CD_CLOCK_312_MHZ   = 5,
 		CD_CLOCK_552_MHZ   = 6,
 		CD_CLOCK_556_8_MHZ = 7,
-		CD_CLOCK_648_MHZ   = 8,
-		CD_CLOCK_652_8_MHZ = 9,
 	} cd_clock;
 
 	/*
diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
index 02d9d76616..c12345f872 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
@@ -876,7 +876,7 @@ typedef struct {
 
 /** Offset 0x0436 - CdClock Frequency selection
   0: 172.8 MHz, 1: 180 MHz, 2: 192 MHz, 3: 307 MHz, 4: 312 MHz, 5: 552 MHz, 6: 556.8 MHz,
-  7: 648 MHz, 8: 652.8 MHz, 0xff: 648 MHz (Default)
+  0xff: 556.8 MHz (Default)
 **/
   UINT8                       CdClock;