tegra132: remove private spin table implementation
Support the generic spin table code instead of having the one-off implementation. BUG=chrome-os-partner:32082 BRANCH=None TEST=Built and booted to kernel w/ smp. Both w/ and w/o secure monitor. Change-Id: I8557298d1a159b70818cbd8864470ff0d8a46fb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8d89af95a7919f0b8acc92d82f3abda965514ccf Original-Change-Id: I24d56a30fdabd7a35ebc28dcc355c675de823a51 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218655 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9085 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin
Patrick Georgi
parent
5add43574d
commit
dec44e9086
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@ -69,7 +69,6 @@ ramstage-y += ../tegra/gpio.c
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ramstage-y += ../tegra/i2c.c
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ramstage-y += ../tegra/pinmux.c
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ramstage-y += ramstage.c
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ramstage-y += spintable.S
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ramstage-y += mmu_operations.c
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ramstage-$(CONFIG_DRIVERS_UART) += uart.c
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ramstage-y += ../tegra/usb.c
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@ -21,11 +21,14 @@
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#define __SOC_NVIDIA_TEGRA132_CHIP_H__
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#include <arch/cache.h>
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#include <soc/addressmap.h>
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#include <stdint.h>
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#define EFAULT 1
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#define EINVAL 2
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struct soc_nvidia_tegra132_config {
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/* Address to monitor if spintable employed. */
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uintptr_t spintable_addr;
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};
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#endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */
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@ -23,6 +23,7 @@
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#include <device/device.h>
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#include <arch/io.h>
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#include <arch/cache.h>
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#include <arch/spintable.h>
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#include <cpu/cpu.h>
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#include <cbmem.h>
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#include <timer.h>
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@ -61,62 +62,6 @@ static void soc_read_resources(device_t dev)
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ram_resource(dev, index++, begin * KiB, size * KiB);
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}
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static void *spintable_entry;
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static uint64_t * const spintable_magic = (void *)(uintptr_t)0x80000008;
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static void spintable_init(void)
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{
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extern void __wait_for_spin_table_request(void);
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const size_t spintable_entry_size = 4096;
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spintable_entry =
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cbmem_add(0x11111111, spintable_entry_size);
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memcpy(spintable_entry, __wait_for_spin_table_request,
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spintable_entry_size);
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/* Ensure the memory location is zero'd out. */
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*spintable_magic = 0;
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dcache_clean_invalidate_by_mva(spintable_magic,
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sizeof(*spintable_magic));
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dcache_clean_invalidate_by_mva(&spintable_entry,
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sizeof(spintable_entry));
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dcache_clean_invalidate_by_mva(spintable_entry, spintable_entry_size);
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dsb();
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}
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static void spintable_wait(void *monitor_address)
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{
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uint32_t sctlr_el2;
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uint32_t spsr_el3;
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uint32_t scr_el3;
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sctlr_el2 = raw_read_sctlr_el2();
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/* Make sure EL2 is in little endian without any caching enabled. */
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sctlr_el2 &= ~(1 << 25);
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sctlr_el2 &= ~(1 << 19);
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sctlr_el2 &= ~(1 << 12);
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sctlr_el2 &= ~0xf;
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raw_write_sctlr_el2(sctlr_el2);
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/* Ensure enter into EL2t with interrupts disabled. */
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spsr_el3 = (1 << 9) | (0xf << 6) | (1 << 3);
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raw_write_spsr_el3(spsr_el3);
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raw_write_elr_el3((uintptr_t)spintable_entry);
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/*
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* Lower exception level is 64 bit. HVC and SMC allowed. EL0 and EL1
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* in non-secure mode. No interrupts routed to EL3.
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*/
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scr_el3 = raw_read_scr_el3();
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scr_el3 |= (1 << 10) | (1 << 8) | (0x3 << 4) | (1 << 0);
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scr_el3 &= ~((0x7 << 1) | (1 << 7) | (1 << 9) | (1 << 13) | (1 << 12));
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raw_write_scr_el3(scr_el3);
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isb();
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asm volatile(
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"mov x0, %0\n\t"
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"eret\n\t" : : "r" (monitor_address) : "x0" );
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}
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static size_t cntrl_total_cpus(void)
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{
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return CONFIG_MAX_CPUS;
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@ -137,16 +82,13 @@ static struct cpu_control_ops cntrl_ops = {
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static void soc_init(device_t dev)
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{
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struct cpu_action action = {
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.run = spintable_wait,
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.arg = spintable_magic,
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};
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struct soc_nvidia_tegra132_config *cfg;
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clock_init_arm_generic_timer();
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spintable_init();
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cfg = dev->chip_info;
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spintable_init((void *)cfg->spintable_addr);
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arch_initialize_cpus(dev, &cntrl_ops);
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arch_run_on_cpu_async(1, &action);
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}
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static void soc_noop(device_t dev)
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@ -1,38 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/asm.h>
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ENTRY(__wait_for_spin_table_request)
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/* Entry here is in EL2 with the magic address in x0. */
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mov x28, x0
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1:
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ldr x27, [x28]
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cmp x27, xzr
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b.ne 2f
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wfe
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b 1b
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2:
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/* Entry into the kernel. */
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mov x0, xzr
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mov x1, xzr
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mov x2, xzr
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mov x3, xzr
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br x27
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ENDPROC(__wait_for_spin_table_request)
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