drivers/mrc_cache: move mrc_cache support to drivers

There's nothing intel-specific about the current mrc_cache support.
It's logic manages saving non-volatile areas into the boot media.
Therefore, expose it to the rest of the system for any and all to
use.

BUG=b:69614064

Change-Id: I3b331c82a102f88912a3e10507a70207fb20aecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/drivers/intel/fsp1_1/romstage.c

@@ -28,11 +28,11 @@
 #include <ec/google/chromeec/ec_commands.h>
 #include <elog.h>
 #include <fsp/romstage.h>
+#include <mrc_cache.h>
 #include <reset.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <smbios.h>
-#include <soc/intel/common/mrc_cache.h>
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>

src/drivers/intel/fsp2_0/memory_init.c

@@ -24,10 +24,10 @@
 #include <fsp/api.h>
 #include <fsp/util.h>
 #include <memrange.h>
+#include <mrc_cache.h>
 #include <program_loading.h>
 #include <reset.h>
 #include <romstage_handoff.h>
-#include <soc/intel/common/mrc_cache.h>
 #include <string.h>
 #include <symbols.h>
 #include <timestamp.h>

src/drivers/mrc_cache/Kconfig

@@ -0,0 +1,31 @@
+config CACHE_MRC_SETTINGS
+	bool "Save cached MRC settings"
+	default n
+
+if CACHE_MRC_SETTINGS
+
+config MRC_SETTINGS_CACHE_BASE
+	hex
+	default 0xfffe0000
+
+config MRC_SETTINGS_CACHE_SIZE
+	hex
+	default 0x10000
+
+config MRC_SETTINGS_PROTECT
+	bool "Enable protection on MRC settings"
+	default n
+
+config HAS_RECOVERY_MRC_CACHE
+	bool
+	default n
+
+config MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+	bool
+	default n
+
+config MRC_SETTINGS_VARIABLE_DATA
+	bool
+	default n
+
+endif # CACHE_MRC_SETTINGS

src/drivers/mrc_cache/Makefile.inc

@@ -0,0 +1,16 @@
+
+romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
+ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
+
+# Create and add the MRC cache to the cbfs image
+ifneq ($(CONFIG_CHROMEOS),y)
+$(obj)/mrc.cache: $(obj)/config.h
+	dd if=/dev/zero count=1 \
+	bs=$(shell printf "%d" $(CONFIG_MRC_SETTINGS_CACHE_SIZE) ) | \
+	tr '\000' '\377' > $@
+
+cbfs-files-$(CONFIG_CACHE_MRC_SETTINGS) += mrc.cache
+mrc.cache-file := $(obj)/mrc.cache
+mrc.cache-position := $(CONFIG_MRC_SETTINGS_CACHE_BASE)
+mrc.cache-type := mrc_cache
+endif

src/soc/intel/apollolake/romstage.c

@@ -36,9 +36,9 @@
 #include <intelblocks/smm.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/pmclib.h>
+#include <mrc_cache.h>
 #include <reset.h>
 #include <soc/cpu.h>
-#include <soc/intel/common/mrc_cache.h>
 #include <soc/iomap.h>
 #include <soc/systemagent.h>
 #include <soc/pci_devs.h>

src/soc/intel/baytrail/romstage/raminit.c

@@ -21,8 +21,8 @@
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <halt.h>
+#include <mrc_cache.h>
 #include <soc/gpio.h>
-#include <soc/intel/common/mrc_cache.h>
 #include <soc/iomap.h>
 #include <soc/iosf.h>
 #include <soc/pci_devs.h>

src/soc/intel/braswell/romstage/romstage.c

@@ -28,13 +28,13 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <elog.h>
+#include <mrc_cache.h>
 #include <romstage_handoff.h>
 #include <string.h>
 #include <timestamp.h>
 #include <reset.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <fsp/util.h>
-#include <soc/intel/common/mrc_cache.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
 #include <soc/iosf.h>

src/soc/intel/broadwell/romstage/raminit.c

@@ -21,13 +21,13 @@
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <lib.h>
+#include <mrc_cache.h>
 #include <string.h>
 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 #endif
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/intel/common/mrc_cache.h>
 #include <soc/iomap.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>

src/soc/intel/common/Kconfig

@@ -8,38 +8,6 @@ if SOC_INTEL_COMMON
 comment "Intel SoC Common Code"
 source "src/soc/intel/common/block/Kconfig"
 
-config CACHE_MRC_SETTINGS
-	bool "Save cached MRC settings"
-	default n
-
-if CACHE_MRC_SETTINGS
-
-config MRC_SETTINGS_CACHE_BASE
-	hex
-	default 0xfffe0000
-
-config MRC_SETTINGS_CACHE_SIZE
-	hex
-	default 0x10000
-
-config MRC_SETTINGS_PROTECT
-	bool "Enable protection on MRC settings"
-	default n
-
-config HAS_RECOVERY_MRC_CACHE
-	bool
-	default n
-
-config MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
-	bool
-	default n
-
-config MRC_SETTINGS_VARIABLE_DATA
-	bool
-	default n
-
-endif # CACHE_MRC_SETTINGS
-
 config DISPLAY_MTRRS
 	bool "MTRRs: Display the MTRR settings"
 	default n

src/soc/intel/common/Makefile.inc

@@ -9,7 +9,6 @@ verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 
 bootblock-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 
-romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
 romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 romstage-y += util.c
 romstage-$(CONFIG_MMA) += mma.c
@@ -19,7 +18,6 @@ postcar-y += util.c
 postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 
 ramstage-y += hda_verb.c
-ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 ramstage-y += util.c
 ramstage-$(CONFIG_MMA) += mma.c
@@ -33,19 +31,6 @@ verstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c
 romstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c
 ramstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c
 
-# Create and add the MRC cache to the cbfs image
-ifneq ($(CONFIG_CHROMEOS),y)
-$(obj)/mrc.cache: $(obj)/config.h
-	dd if=/dev/zero count=1 \
-	bs=$(shell printf "%d" $(CONFIG_MRC_SETTINGS_CACHE_SIZE) ) | \
-	tr '\000' '\377' > $@
-
-cbfs-files-$(CONFIG_CACHE_MRC_SETTINGS) += mrc.cache
-mrc.cache-file := $(obj)/mrc.cache
-mrc.cache-position := $(CONFIG_MRC_SETTINGS_CACHE_BASE)
-mrc.cache-type := mrc_cache
-endif
-
 ifeq ($(CONFIG_MMA),y)
 MMA_BLOBS_PATH = $(call strip_quotes,$(CONFIG_MMA_BLOBS_PATH))
 MMA_TEST_NAMES = $(notdir $(wildcard $(MMA_BLOBS_PATH)/tests/*))