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soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE 

CPX-SP processor has 2 IMC, there are 3 channels per IMC,
2 DIMMs per channel.

It supports DDR4.

Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly.

Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jonathan Zhang 2020-07-27 15:26:30 -07:00 committed by Angel Pons
parent 1343bc394b
commit decf7dc4f8
1 changed files with 11 additions and 0 deletions
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11
src/soc/intel/xeon_sp/cpx/Kconfig
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@ -68,4 +68,15 @@ config SOC_INTEL_COMMON_BLOCK_P2SB
select CACHE_MRC_SETTINGS
# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel
# Default value is set to one socket, full config.
config DIMM_MAX
int
default 12
# DDR4
config DIMM_SPD_SIZE
int
default 512
endif