mb/google/brya/var/dochi: update gpio settings
Configure GPIOs according to schematics revision 20230923. TEST=emerge-brya coreboot Change-Id: I10bd1b72c9b0299b8d29ab642fddb5f0c4727652 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
This commit is contained in:
Morris Hsu
Felix Held
parent
ff63106dec
commit
ded03d55cc
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@ -1,2 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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romstage-y += memory.c
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ramstage-y += gpio.c
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@ -0,0 +1,207 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A6 : ESPI_ALERT1# ==> NC */
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PAD_NC(GPP_A6, NONE),
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/* A7 : SRCCLK_OE7# ==> NC */
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PAD_NC(GPP_A7, NONE),
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/* A8 : SRCCLKREQ7# ==> NC */
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PAD_NC(GPP_A8, NONE),
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/* A12 : SATAXPCIE1 ==> NC */
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PAD_NC(GPP_A12, NONE),
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/* A15 : USB_OC2# ==> NC */
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PAD_NC(GPP_A15, NONE),
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/* A19 : DDSP_HPD1 ==> NC */
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PAD_NC(GPP_A19, NONE),
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/* A20 : DDSP_HPD2 ==> NC */
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PAD_NC(GPP_A20, NONE),
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/* B3 : PROC_GP2 ==> NC */
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PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
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/* D3 : ISH_GP3 ==> NC */
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PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
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/* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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/* D6 : SRCCLKREQ1# ==> APU_PEN_DETECT_ODL */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_D6, NONE, PLTRST),
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/* D7 : SRCCLKREQ2# ==> NC */
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PAD_NC(GPP_D7, NONE),
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/* D8 : SRCCLKREQ3# ==> NC */
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PAD_NC(GPP_D8, NONE),
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/* D9 : ISH_SPI_CS# ==> NC */
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PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
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/* D16 : ISH_UART0_CTS# ==> NC */
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PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
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/* D17 : UART1_RXD ==> APU_PEN_DETECT_ODL */
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PAD_CFG_GPI_SCI_LOCK(GPP_D17, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG),
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/* D18 : UART1_TXD ==> NC */
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PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
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/* E0 : SATAXPCIE0 ==> NC */
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PAD_NC(GPP_E0, NONE),
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/* E3 : PROC_GP0 ==> NC */
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PAD_NC(GPP_E3, NONE),
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/* E4 : SATA_DEVSLP0 ==> NC */
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PAD_NC(GPP_E4, NONE),
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/* E7 : PROC_GP1 ==> NC */
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PAD_NC(GPP_E7, NONE),
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/* E10 : THC0_SPI1_CS# ==> NC */
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PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
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/* E17 : THC0_SPI1_INT# ==> NC */
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PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
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/* E18 : DDP1_CTRLCLK ==> NC */
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PAD_NC(GPP_E18, NONE),
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/* E20 : DDP2_CTRLCLK ==> NC */
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PAD_NC(GPP_E20, NONE),
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/* F6 : CNV_PA_BLANKING ==> NC */
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PAD_NC(GPP_F6, NONE),
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/* F20 : EXT_PWR_GATE# ==> NC */
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PAD_NC(GPP_F20, NONE),
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/* F21 : EXT_PWR_GATE2# ==> NC */
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PAD_NC(GPP_F21, NONE),
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/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG),
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/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
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/* H8 : I2C4_SDA ==> NC */
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PAD_NC(GPP_H8, NONE),
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/* H9 : I2C4_SCL ==> NC */
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PAD_NC(GPP_H9, NONE),
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/* H12 : I2C7_SDA ==> NC */
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PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
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/* H13 : I2C7_SCL ==> NC */
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PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
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/* H19 : SRCCLKREQ4# ==> EMMC_CLKREQ_ODL */
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PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
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/* H20 : IMGCLKOUT1 ==> NC */
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PAD_NC(GPP_H20, NONE),
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/* H21 : IMGCLKOUT2 ==> NC */
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PAD_NC(GPP_H21, NONE),
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/* H22 : IMGCLKOUT3 ==> NC */
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PAD_NC(GPP_H22, NONE),
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/* H23 : SRCCLKREQ5# ==> NC */
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PAD_NC(GPP_H23, NONE),
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/* R4 : HDA_RST# ==> DMIC_CLK0_R */
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PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
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/* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
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PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
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/* R6 : I2S2_TXD ==> DMIC_CLK1_R */
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PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
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/* R7 : I2S2_RXD ==> DMIC_DATA1_R */
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PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
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/* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */
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PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
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/* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */
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PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
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/* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */
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PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
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/* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */
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PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
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/* GPD11: LANPHYC ==> NC */
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PAD_NC(GPD11, NONE),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 0, DEEP),
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/*
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* D1 : ISH_GP1 ==> FP_RST_ODL
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* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
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* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
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* early on in bootblock, followed by enabling of power. Reset signal is deasserted
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* later on in ramstage. Since reset signal is asserted in bootblock, it results in
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* FPMCU not working after a S3 resume. This is a known issue.
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*/
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PAD_CFG_GPO(GPP_D1, 0, DEEP),
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/* D2 : ISH_GP2 ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_D11, 1, DEEP),
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/* E0 : SATAXPCIE0 ==> NC */
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PAD_NC(GPP_E0, NONE),
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/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_E13, NONE, DEEP),
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* CPU PCIe VGPIO for PEG60 */
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
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};
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static const struct pad_config romstage_gpio_table[] = {
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 1, DEEP),
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/* Enable touchscreen, hold in reset */
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/* C0 : SMBCLK ==> EN_PP3300_TCHSCR */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C1 : SMBDATA ==> USI_RST_L */
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PAD_CFG_GPO(GPP_C1, 0, DEEP),
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/* D1 : ISH_GP1 ==> FP_RST_ODL */
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PAD_CFG_GPO(GPP_D1, 0, DEEP),
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/* D2 : ISH_GP2 ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_D2, 0, DEEP),
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};
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(romstage_gpio_table);
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return romstage_gpio_table;
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}
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