mb/intel/kblrvp: Factor out `HeciEnabled`
RVP8 does not set it, and the other variants set it to zero. So, factor it out. Tested with BUILD_TIMELESS=1, all four variants do not change. Change-Id: I67c958af2dc955d07b895dc93fbe2232dbd48d34 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43908 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -23,6 +23,7 @@ chip soc/intel/skylake
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register "dptf_enable" = "1"
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# FSP Configuration
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register "HeciEnabled" = "0"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsSdCardEnabled" = "2"
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register "SkipExtGfxScan" = "1"
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@ -9,7 +9,6 @@ chip soc/intel/skylake
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# FSP Configuration
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "0"
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register "HeciEnabled" = "0"
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register "PmTimerDisabled" = "1"
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register "Cio2Enable" = "1"
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register "SaImguEnable" = "1"
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@ -13,7 +13,6 @@ chip soc/intel/skylake
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register "gen2_dec" = "0x000c0201"
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# FSP Configuration
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register "HeciEnabled" = "0"
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register "PmTimerDisabled" = "1"
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# VR Settings Configuration for 4 Domains
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@ -7,7 +7,6 @@ chip soc/intel/skylake
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# FSP Configuration
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register "ScsEmmcHs400Enabled" = "0"
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register "ScsSdCardEnabled" = "0"
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register "HeciEnabled" = "0"
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register "PmTimerDisabled" = "0"
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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