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mb/intel/kblrvp: Factor out `HeciEnabled` 

RVP8 does not set it, and the other variants set it to zero. So, factor
it out.

Tested with BUILD_TIMELESS=1, all four variants do not change.

Change-Id: I67c958af2dc955d07b895dc93fbe2232dbd48d34
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43908
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-07-26 17:17:24 +02:00
parent 33aa115574
commit defdc8539b
4 changed files with 1 additions and 3 deletions
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1
src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
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@ -23,6 +23,7 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
register "HeciEnabled" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "SkipExtGfxScan" = "1"

1
src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
View File

@ -9,7 +9,6 @@ chip soc/intel/skylake
# FSP Configuration
register "DspEnable" = "1"
register "IoBufferOwnership" = "0"
register "HeciEnabled" = "0"
register "PmTimerDisabled" = "1"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"

1
src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
View File

@ -13,7 +13,6 @@ chip soc/intel/skylake
register "gen2_dec" = "0x000c0201"
# FSP Configuration
register "HeciEnabled" = "0"
register "PmTimerDisabled" = "1"
# VR Settings Configuration for 4 Domains

1
src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
View File

@ -7,7 +7,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "HeciEnabled" = "0"
register "PmTimerDisabled" = "0"
register "serirq_mode" = "SERIRQ_CONTINUOUS"