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intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL 

This is a PCI standard register, no need to alias its
definitions under different names.

Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2019-09-21 18:35:37 +03:00
parent a84a7340b6
commit df128a55b1
21 changed files with 65 additions and 91 deletions
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4
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -247,9 +247,9 @@ void mainboard_romstage_entry(void)
enable_lapic();
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET);
udelay(200 * 1000);
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0);
ich7_enable_lpc();
early_superio_config_w83627thg();

4
src/mainboard/roda/rk886ex/romstage.c
View File

@ -210,9 +210,9 @@ void mainboard_romstage_entry(void)
enable_lapic();
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET);
udelay(200 * 1000);
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0);
ich7_enable_lpc();
early_superio_config();

4
src/northbridge/intel/haswell/haswell.h
View File

@ -108,10 +108,6 @@
#define GLBIOTLBINV (1 << 1)
#define GLBCTXTINV (1 << 0)
/* Device 0:1.0 PCI configuration space (PCI Express) */
#define BCTRL1 0x3e /* 16bit */
/* Device 0:2.0 PCI configuration space (Graphics Device) */

41
src/northbridge/intel/i945/early_init.c
View File

@ -546,13 +546,13 @@ static void i945_setup_pci_express_x16(void)
*/
/* First we reset the secondary bus */
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
reg16 |= (1 << 6); /* SRESET */
pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL);
reg16 |= PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16);
/* Read back and clear reset bit. */
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
reg16 &= ~(1 << 6); /* SRESET */
pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; /* SRESET */
pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16);
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS);
printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
@ -610,12 +610,11 @@ static void i945_setup_pci_express_x16(void)
reg32 |= 1;
pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32);
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
reg16 |= (1 << 6);
pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
reg16 &= ~(1 << 6);
pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL);
reg16 |= PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16);
reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16);
printk(BIOS_DEBUG, "PCIe link training ...");
timeout = 0x7ffff;
@ -663,9 +662,9 @@ static void i945_setup_pci_express_x16(void)
pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32);
/* Set VGA enable bit in PCIe bridge */
reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), BCTRL1);
reg16 |= (1 << 3);
pci_write_config16(PCI_DEV(0, 0x1, 0), BCTRL1, reg16);
reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), PCI_BRIDGE_CONTROL);
reg16 |= PCI_BRIDGE_CTL_VGA;
pci_write_config16(PCI_DEV(0, 0x1, 0), PCI_BRIDGE_CONTROL, reg16);
}
/* Enable GPEs */
@ -776,17 +775,17 @@ disable_pciexpress_x16_link:
MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
reg16 |= (1 << 6);
pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL);
reg16 |= PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16);
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224);
reg32 |= (1 << 8);
pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
reg16 &= ~(1 << 6);
pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16);
printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
timeout = 0x7fffff;

1
src/northbridge/intel/i945/i945.h
View File

@ -86,7 +86,6 @@
#define SBUSN1 0x19 /* 8bit */
#define SUBUSN1 0x1a /* 8bit */
#define SSTS1 0x1e /* 16bit */
#define BCTRL1 0x3e /* 16bit */
#define PEG_CAP 0xa2 /* 16bit */
#define DSTS 0xaa /* 16bit */
#define SLOTCAP 0xb4 /* 32bit */

4
src/northbridge/intel/nehalem/nehalem.h
View File

@ -153,10 +153,6 @@ typedef struct {
#define SKPAD 0xdc /* Scratchpad Data */
/* Device 0:1.0 PCI configuration space (PCI Express) */
#define BCTRL1 0x3e /* 16bit */
/* Device 0:2.0 PCI configuration space (Graphics Device) */

1
src/northbridge/intel/pineview/pineview.h
View File

@ -84,7 +84,6 @@
/* Device 0:1.0 PCI configuration space (PCI Express) */
#define BCTRL1 0x3e /* 16bit */
#define PEGSTS 0x214 /* 32bit */
/* Device 0:2.0 PCI configuration space (Graphics Device) */

4
src/northbridge/intel/sandybridge/sandybridge.h
View File

@ -101,10 +101,6 @@ enum platform_type {
#define SKPAD 0xdc /* Scratchpad Data */
/* Device 0:1.0 PCI configuration space (PCI Express) */
#define BCTRL1 0x3e /* 16bit */
/* Device 0:2.0 PCI configuration space (Graphics Device) */

8
src/soc/intel/broadwell/pcie.c
View File

@ -604,10 +604,10 @@ static void pch_pcie_init(struct device *dev)
/* Set Cache Line Size to 0x10 */
pci_write_config8(dev, 0x0c, 0x10);
reg16 = pci_read_config16(dev, 0x3e);
reg16 &= ~(1 << 0); /* disable parity error response */
reg16 |= (1 << 2); /* ISA enable */
pci_write_config16(dev, 0x3e, reg16);
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_PARITY;
reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);

3
src/soc/intel/common/block/pcie/pcie.c
View File

@ -38,7 +38,8 @@ static void pch_pcie_init(struct device *dev)
pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE);
/* disable parity error response, enable ISA */
pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2);
pci_update_config16(dev, PCI_BRIDGE_CONTROL,
~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA);
if (CONFIG(PCIE_DEBUG_INFO)) {
printk(BIOS_SPEW, " MBL = 0x%08x\n",

4
src/southbridge/intel/bd82x6x/pch.h
View File

@ -101,10 +101,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap);
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
#define BCTRL 0x3e
#define SBR (1 << 6)
#define SEE (1 << 1)
#define PERE (1 << 0)
#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)

9
src/southbridge/intel/bd82x6x/pci.c
View File

@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "pch.h"
@ -36,10 +37,10 @@ static void pci_init(struct device *dev)
pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
reg16 = pci_read_config16(dev, BCTRL);
reg16 &= ~(1 << 0);
reg16 &= ~(1 << 1);
pci_write_config16(dev, BCTRL, reg16);
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_PARITY;
reg16 &= ~PCI_BRIDGE_CTL_SERR;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Master Latency Count must be set to 0x04! */
reg8 = pci_read_config8(dev, SMLT);

10
src/southbridge/intel/bd82x6x/pcie.c
View File

@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
@ -232,11 +233,10 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
reg16 = pci_read_config16(dev, 0x3e);
reg16 &= ~(1 << 0); /* disable parity error response */
// reg16 &= ~(1 << 1); /* disable SERR */
reg16 |= (1 << 2); /* ISA enable */
pci_write_config16(dev, 0x3e, reg16);
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_PARITY;
reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);

4
src/southbridge/intel/i82801gx/i82801gx.h
View File

@ -59,10 +59,6 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
#define BCTRL 0x3e
#define SBR (1 << 6)
#define SEE (1 << 1)
#define PERE (1 << 0)
#define ICH_PCIE_DEV_SLOT 28

9
src/southbridge/intel/i82801gx/pci.c
View File

@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "i82801gx.h"
@ -35,10 +36,10 @@ static void pci_init(struct device *dev)
pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
reg16 = pci_read_config16(dev, BCTRL);
reg16 &= ~(1 << 0);
reg16 &= ~(1 << 1);
pci_write_config16(dev, BCTRL, reg16);
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_PARITY;
reg16 &= ~PCI_BRIDGE_CTL_SERR;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Master Latency Count must be set to 0x04! */
reg8 = pci_read_config8(dev, SMLT);

10
src/southbridge/intel/i82801gx/pcie.c
View File

@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "chip.h"
@ -67,11 +68,10 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
reg16 = pci_read_config16(dev, 0x3e);
reg16 &= ~(1 << 0); /* disable parity error response */
// reg16 &= ~(1 << 1); /* disable SERR */
reg16 |= (1 << 2); /* ISA enable */
pci_write_config16(dev, 0x3e, reg16);
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_PARITY;
reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Enable IO xAPIC on this PCIe port */
reg32 = pci_read_config32(dev, 0xd8);

9
src/southbridge/intel/i82801ix/pcie.c
View File

@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
@ -41,10 +42,10 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
reg16 = pci_read_config16(dev, 0x3e);
reg16 &= ~(1 << 0); /* disable parity error response */
reg16 |= (1 << 2); /* ISA enable */
pci_write_config16(dev, 0x3e, reg16);
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_PARITY;
reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Enable IO xAPIC on this PCIe port */
reg32 = pci_read_config32(dev, 0xd8);

9
src/southbridge/intel/i82801jx/pcie.c
View File

@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
@ -41,10 +42,10 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
reg16 = pci_read_config16(dev, 0x3e);
reg16 &= ~(1 << 0); /* disable parity error response */
reg16 |= (1 << 2); /* ISA enable */
pci_write_config16(dev, 0x3e, reg16);
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_PARITY;
reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Enable IO xAPIC on this PCIe port */
reg32 = pci_read_config32(dev, 0xd8);

4
src/southbridge/intel/ibexpeak/pch.h
View File

@ -82,10 +82,6 @@ void pch_enable(struct device *dev);
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
#define BCTRL 0x3e
#define SBR (1 << 6)
#define SEE (1 << 1)
#define PERE (1 << 0)
#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)

4
src/southbridge/intel/lynxpoint/pch.h
View File

@ -195,10 +195,6 @@ void mainboard_config_superio(void);
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
#define BCTRL 0x3e
#define SBR (1 << 6)
#define SEE (1 << 1)
#define PERE (1 << 0)
/* Power Management Control and Status */
#define PCH_PCS 0x84

10
src/southbridge/intel/lynxpoint/pcie.c
View File

@ -19,6 +19,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
@ -684,11 +685,10 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
reg16 = pci_read_config16(dev, 0x3e);
reg16 &= ~(1 << 0); /* disable parity error response */
// reg16 &= ~(1 << 1); /* disable SERR */
reg16 |= (1 << 2); /* ISA enable */
pci_write_config16(dev, 0x3e, reg16);
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_PARITY;
reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);