soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h
Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34085 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -27,12 +27,11 @@
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#include <soc/nvs.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/soc_chip.h>
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#include <string.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <wrdd.h>
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#include "chip.h"
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/*
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* List of supported C-states in this processor.
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*/
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@ -26,8 +26,7 @@
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#include <soc/itss.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include "chip.h"
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#include <soc/soc_chip.h>
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#if CONFIG(HAVE_ACPI_TABLES)
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const char *soc_acpi_name(const struct device *dev)
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@ -31,8 +31,7 @@
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/smm.h>
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#include "chip.h"
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#include <soc/soc_chip.h>
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static void soc_fsp_load(void)
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{
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@ -29,8 +29,7 @@
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#include <soc/irq.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include "chip.h"
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#include <soc/soc_chip.h>
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/*
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* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
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@ -30,11 +30,10 @@
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <soc/soc_chip.h>
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#include <soc/systemagent.h>
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#include <stdlib.h>
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#include "chip.h"
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#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
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#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
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#define CAM_CLK_EN (1 << 1)
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@ -13,7 +13,6 @@
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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@ -23,6 +22,7 @@
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#include <soc/intel/common/vbt.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/soc_chip.h>
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#include <string.h>
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#include <intelblocks/mp_init.h>
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#include <fsp/ppi/mp_service_ppi.h>
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@ -19,8 +19,7 @@
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#include <device/device.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include "../../chip.h"
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#include <soc/soc_chip.h>
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void mainboard_silicon_init_params(FSP_S_CONFIG *params);
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void soc_init_pre_device(void *chip_info);
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@ -23,11 +23,10 @@
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#include <intelblocks/systemagent.h>
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#include <soc/pci_devs.h>
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#include <soc/smm.h>
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#include <soc/soc_chip.h>
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#include <soc/systemagent.h>
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#include <stdlib.h>
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#include "chip.h"
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void smm_region(void **start, size_t *size)
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{
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*start = (void *)sa_get_tseg_base();
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@ -23,8 +23,7 @@
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#include <intelblocks/rtc.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include "chip.h"
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#include <soc/soc_chip.h>
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/*
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* Set which power state system will be after reapplying
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@ -37,10 +37,9 @@
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <soc/soc_chip.h>
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#include <security/vboot/vbnv.h>
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#include "chip.h"
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/*
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* SMI
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*/
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@ -14,12 +14,12 @@
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*/
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#include <assert.h>
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#include <chip.h>
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#include <console/console.h>
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#include <fsp/util.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <soc/soc_chip.h>
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static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_icelake_config *config)
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@ -27,11 +27,10 @@
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/romstage.h>
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#include <soc/soc_chip.h>
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#include <string.h>
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#include <timestamp.h>
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#include "../chip.h"
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#define FSP_SMBIOS_MEMORY_INFO_GUID \
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{ \
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0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
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@ -14,7 +14,7 @@
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*/
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#include <intelblocks/sd.h>
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#include "chip.h"
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#include <soc/soc_chip.h>
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int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, struct device *dev)
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{
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@ -23,8 +23,7 @@
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include "chip.h"
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#include <soc/soc_chip.h>
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#define CSME0_FBE 0xf
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#define CSME0_BAR 0x0
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@ -31,8 +31,8 @@
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/smm.h>
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#include <soc/soc_chip.h>
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#include <soc/systemagent.h>
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#include "chip.h"
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/* This gets filled in and used during relocation. */
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static struct smm_relocation_params smm_reloc_params;
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