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MCP55: Add TINY_BOOTBLOCK support. 

Also, move CONFIG_HT_CHAIN_END_UNITID_BASE #ifdef block to mcp55.h to make
the build work (but this is a good idea anyway, as it's used in
multiple files).

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-11-25 09:03:55 +00:00
parent 48ae6086da
commit df323fcefd
17 changed files with 47 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -81,7 +81,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c" #include "cpu/amd/model_fxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c" #include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
@ -124,7 +123,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
mcp55_enable_rom();
} }
if (bist == 0) if (bist == 0)

2
src/mainboard/msi/ms7260/romstage.c
View File

@ -83,7 +83,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c" #include "cpu/amd/model_fxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c" #include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
@ -125,7 +124,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Allow the HT devices to be found. */ /* Allow the HT devices to be found. */
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
mcp55_enable_rom();
} }
if (bist == 0) if (bist == 0)

2
src/mainboard/msi/ms9282/romstage.c
View File

@ -96,7 +96,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
// Disabled until it's actually used: // Disabled until it's actually used:
// #include "cpu/amd/model_fxx/fidvid.c" // #include "cpu/amd/model_fxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c" #include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
@ -138,7 +137,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
mcp55_enable_rom();
} }
if (bist == 0) { if (bist == 0) {

2
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -78,7 +78,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/microcode/microcode.c" #include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/init_cpus.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c" #include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
@ -117,7 +116,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
set_bsp_node_CHtExtNodeCfgEn(); set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
mcp55_enable_rom();
} }
post_code(0x30); post_code(0x30);

2
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -82,7 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c" #include "cpu/amd/model_fxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c" #include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
@ -124,7 +123,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
mcp55_enable_rom();
} }
if (bist == 0) if (bist == 0)

2
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -131,7 +131,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c" #include "cpu/amd/model_fxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c" #include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
@ -189,7 +188,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
mcp55_enable_rom();
} }
if (bist == 0) if (bist == 0)

2
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -72,7 +72,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c" #include "cpu/amd/model_fxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c" #include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
@ -118,7 +117,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
mcp55_enable_rom();
} }
if (bist == 0) if (bist == 0)

2
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -69,7 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/microcode/microcode.c" #include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/init_cpus.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c" #include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
@ -117,7 +116,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
set_bsp_node_CHtExtNodeCfgEn(); set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
mcp55_enable_rom();
} }
post_code(0x30); post_code(0x30);

2
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -75,7 +75,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/microcode/microcode.c" #include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/init_cpus.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c" #include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
@ -168,7 +167,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
set_bsp_node_CHtExtNodeCfgEn(); set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
mcp55_enable_rom();
} }
post_code(0x30); post_code(0x30);

2
src/mainboard/tyan/s2912/romstage.c
View File

@ -82,7 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c" #include "cpu/amd/model_fxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c" #include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
@ -125,7 +124,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
mcp55_enable_rom();
} }
if (bist == 0) if (bist == 0)

2
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -79,7 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/microcode/microcode.c" #include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/init_cpus.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c" #include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
@ -123,7 +122,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
set_bsp_node_CHtExtNodeCfgEn(); set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
mcp55_enable_rom();
} }
post_code(0x30); post_code(0x30);

5
src/southbridge/nvidia/mcp55/Kconfig
View File

@ -2,9 +2,14 @@ config SOUTHBRIDGE_NVIDIA_MCP55
bool bool
select HAVE_USBDEBUG select HAVE_USBDEBUG
select IOAPIC select IOAPIC
select TINY_BOOTBLOCK
if SOUTHBRIDGE_NVIDIA_MCP55 if SOUTHBRIDGE_NVIDIA_MCP55
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/nvidia/mcp55/bootblock.c"
config ID_SECTION_OFFSET config ID_SECTION_OFFSET
hex hex
default 0x80 default 0x80

26
src/southbridge/nvidia/mcp55/bootblock.c Normal file
View File

@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
static void bootblock_southbridge_init(void)
{
mcp55_enable_rom();
}

2
src/southbridge/nvidia/mcp55/chip.h
View File

@ -22,6 +22,8 @@
#ifndef MCP55_CHIP_H #ifndef MCP55_CHIP_H
#define MCP55_CHIP_H #define MCP55_CHIP_H
#include <device/device.h>
struct southbridge_nvidia_mcp55_config struct southbridge_nvidia_mcp55_config
{ {
unsigned int ide0_enable : 1; unsigned int ide0_enable : 1;

12
src/southbridge/nvidia/mcp55/mcp55.h
View File

@ -22,13 +22,21 @@
#ifndef MCP55_H #ifndef MCP55_H
#define MCP55_H #define MCP55_H
#include "chip.h" #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
#ifndef __PRE_RAM__ #ifndef __PRE_RAM__
#include "chip.h"
void mcp55_enable(device_t dev); void mcp55_enable(device_t dev);
extern struct pci_operations mcp55_pci_ops; extern struct pci_operations mcp55_pci_ops;
#else #else
#if !defined(__ROMCC__)
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
#endif
void mcp55_enable_usbdebug(unsigned int port); void mcp55_enable_usbdebug(unsigned int port);
#endif
#endif
#endif /* MCP55_H */ #endif /* MCP55_H */

9
src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
View File

@ -21,11 +21,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #include <stdint.h>
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #include <arch/io.h>
#else #include <arch/romcc_io.h>
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #include "mcp55.h"
#endif
static void mcp55_enable_rom(void) static void mcp55_enable_rom(void)
{ {

6
src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
View File

@ -28,12 +28,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include "mcp55.h" #include "mcp55.h"
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
void set_debug_port(unsigned int port) void set_debug_port(unsigned int port)
{ {
u32 dword; u32 dword;