A number of cleanups for 440BX raminit code.
Resolves a number of TODOs items within, and clarified a number of other TODOs. Change register_values[] from long to u8 (byte). For what we are doing this is sufficient and makes it only 1/4 the size. Remove a hard-coding of SDRAMC register that is redundant and now incorrect, now that SDRAMC is conditioned on SDRAMPWR_4DIMM Kconfig and set through register_values[]. This fixes all boards with 3 DIMM slots (e.g. ASUS P2B, A-Trend ATC-6220). RPS registers are now set in runtime code; remove it from register_values[] table. Bring DUMPNORTH() back. The code it refers to is still there. Move #define of NB up so the DUMPNORTH() macro can use it. Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Keith Hui
Uwe Hermann
parent
0865b4d9c0
commit
df35cdc198
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@ -29,15 +29,15 @@
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Macros and definitions.
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-----------------------------------------------------------------------------*/
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#define NB PCI_DEV(0, 0, 0)
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/* Debugging macros. */
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#if CONFIG_DEBUG_RAM_SETUP
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#define PRINT_DEBUG(x) print_debug(x)
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#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
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#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
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#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
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// no dump_pci_device in src/northbridge/intel/i440bx
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// #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
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#define DUMPNORTH()
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#define DUMPNORTH() dump_pci_device(NB)
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#else
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#define PRINT_DEBUG(x)
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#define PRINT_DEBUG_HEX8(x)
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@ -46,8 +46,6 @@ Macros and definitions.
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#define DUMPNORTH()
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#endif
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#define NB PCI_DEV(0, 0, 0)
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/* SDRAMC[7:5] - SDRAM Mode Select (SMS). */
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#define RAM_COMMAND_NORMAL 0x0
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#define RAM_COMMAND_NOP 0x1
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@ -70,7 +68,7 @@ static const uint32_t refresh_rate_map[] = {
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};
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/* Table format: register, bitmask, value. */
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static const long register_values[] = {
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static const u8 register_values[] = {
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/* NBXCFG - NBX Configuration Register
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* 0x50 - 0x53
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*
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@ -131,9 +129,8 @@ static const long register_values[] = {
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* 0 = A7# is sampled asserted (i.e., 0)
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* [01:00] Reserved
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*/
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// TODO
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NBXCFG + 0, 0x00, 0x0c,
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// NBXCFG + 1, 0x00, 0xa0,
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// TODO: Bit 15 should be 0 for multiprocessor boards
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NBXCFG + 1, 0x00, 0x80,
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NBXCFG + 2, 0x00, 0x00,
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NBXCFG + 3, 0x00, 0xff,
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@ -143,7 +140,12 @@ static const long register_values[] = {
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*
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* [7:6] Reserved
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* [5:5] Module Mode Configuration (MMCONFIG)
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* TODO
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* The combination of SDRAMPWR and this bit (which is set by an
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* external strapping option) determine how CKE works.
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* SDRAMPWR MMCONFIG
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* 0 0 = 3 DIMM, CKE0[5:0] driven
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* X 1 = 3 DIMM, CKE0 only
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* 1 0 = 4 DIMM, GCKE only
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* [4:3] DRAM Type (DT)
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* 00 = EDO
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* 01 = SDRAM
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@ -252,12 +254,25 @@ static const long register_values[] = {
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* Sets the row page size for SDRAM. For EDO memory, the page
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* size is fixed at 2 KB.
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*
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* [15:0] Page Size (PS)
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* TODO
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* Bits[1:0] Page Size
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* 00 2 KB
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* 01 4 KB
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* 10 8 KB
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* 11 Reserved
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*
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* RPS bits Corresponding DRB register
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* [01:00] DRB[0], row 0
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* [03:02] DRB[1], row 1
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* [05:04] DRB[2], row 2
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* [07:06] DRB[3], row 3
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* [09:08] DRB[4], row 4
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* [11:10] DRB[5], row 5
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* [13:12] DRB[6], row 6
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* [15:14] DRB[7], row 7
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*/
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// TODO
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RPS + 0, 0x00, 0x00,
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RPS + 1, 0x00, 0x00,
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/* Power on defaults to 2KB. Will be set later. */
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// RPS + 0, 0x00, 0x00,
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// RPS + 1, 0x00, 0x00,
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/* SDRAMC - SDRAM Control Register
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* 0x76 - 0x77
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@ -266,8 +281,7 @@ static const long register_values[] = {
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* [09:08] Idle/Pipeline DRAM Leadoff Timing (IPDLT)
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* 00 = Illegal
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* 01 = Add a clock delay to the lead-off clock count
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* 10 = Illegal
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* 11 = Illegal
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* 1x = Illegal
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* [07:05] SDRAM Mode Select (SMS)
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* 000 = Normal SDRAM Operation (default)
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* 001 = NOP Command Enable
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@ -304,7 +318,9 @@ static const long register_values[] = {
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* 0x78 - 0x79
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*
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* [15:08] Banks per Row (BPR)
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* TODO
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* Each bit in this field corresponds to one row of the memory
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* array. Bit 15 corresponds to row 7 while bit 8 corresponds
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* to row 0. Bits for empty rows are "don't care".
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* 0 = 2 banks
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* 1 = 4 banks
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* [07:05] Reserved
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@ -320,7 +336,6 @@ static const long register_values[] = {
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* 0111 = 32 clocks
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* 1xxx = Infinite (pages are not closed for idle condition)
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*/
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// TODO
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PGPOL + 0, 0x00, 0x00,
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PGPOL + 1, 0x00, 0xff,
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@ -354,7 +369,6 @@ static const long register_values[] = {
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/* Enable normal refresh and the gated clock. */
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// TODO: Only do this later?
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// PMCR, 0x00, 0x14,
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// PMCR, 0x00, 0x10,
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PMCR, 0x00, 0x00,
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/* Enable SCRR.SRRAEN and let BX choose the SRR. */
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@ -458,11 +472,11 @@ static void set_dram_buffer_strength(void)
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}
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}
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/* Algorithm bitmap for programming MBSC[39:0] and MBFS[23:0]
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/* Algorithm bitmap for programming MBSC[39:0] and MBFS[23:0].
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*
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* 440BX datasheet says buffer frequency is independent from bus frequency
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* and mismatch both ways are possible. This is how it is programmed
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* in ASUS P2B-LS.
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* The 440BX datasheet says buffer frequency is independent from bus
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* frequency and mismatch both ways are possible. This is how it is
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* programmed in the ASUS P2B-LS mainboard.
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*
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* There are four main conditions to check when programming DRAM buffer
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* frequency and strength:
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@ -523,7 +537,8 @@ static void set_dram_buffer_strength(void)
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* +--------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA#
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* MBSC[47:40] and MBFS[23] are reserved.
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*
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* This algorithm is checked against P2B-LS factory BIOS. It has 4 DIMM slots.
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* This algorithm is checked against the ASUS P2B-LS (which has
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* 4 DIMM slots) factory BIOS.
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* Therefore it assumes a board with 4 slots, and will need testing
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* on boards with 3 DIMM slots.
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*/
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@ -946,17 +961,14 @@ static void sdram_set_spd_registers(void)
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/* Setup DRAM row boundary registers and other attributes. */
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set_dram_row_attributes();
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/* TODO: Set SDRAMC. */
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pci_write_config16(NB, SDRAMC, 0x0010); /* SDRAMPWR=1: 4 DIMM config */
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/* TODO */
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/* Setup DRAM buffer strength. */
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set_dram_buffer_strength();
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/* TODO: Set PMCR? */
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// pci_write_config8(NB, PMCR, 0x14);
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pci_write_config8(NB, PMCR, 0x10);
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/* TODO? */
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/* TODO: This is for EDO memory only. */
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pci_write_config8(NB, DRAMT, 0x03);
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}
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