From df499b53c3ce8acbb4c303b2041d09cb526e252e Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 27 Aug 2015 13:18:53 -0500 Subject: [PATCH] nb/amd/amdmct/mct_ddr3: Fix a minor RDIMM CS select error Change-Id: I4cdfeec887813c17edcdee8858222414fb19b72c Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/12057 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c index 01061a7335..a63fe2e552 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c @@ -232,7 +232,7 @@ void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat, for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel ++, MrsChipSel ++) { if (pDCTstat->CSPresent & (1 << MrsChipSel)) { val = Get_NB32_DCT(dev, dct, 0xa8); - val &= ~(0xf << 8); + val &= ~(0xff << 8); switch (MrsChipSel) { case 0: @@ -279,7 +279,7 @@ void FreqChgCtrlWrd(struct MCTStatStruc *pMCTstat, /* 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. */ val = Get_NB32_DCT(dev, dct, 0xa8); val &= ~(0xff << 8); - val |= (0x3 << (MrsChipSel & 0xfe)) << 8; + val |= (0x3 << (MrsChipSel & ~0x1)) << 8; Set_NB32_DCT(dev, dct, 0xa8, val); /* Resend control word 10 */