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google/kahlee: Set USB OC pins 

Set the USB over current pins for the Grunt baseboard and
Kahlee mainboard. Removes the ACPI ASL OC code, which is not
used on Stoney Ridge SOC.

BUG=b:69229635
TEST=Build and boot Kahlee. Not tested with OC test fixture.

Change-Id: I5a9b3409d9c91b89fd02f8eecf9e04c435f14342
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Marc Jones 2017-11-29 20:07:46 -07:00 committed by Martin Roth
parent fb4c7d250f
commit df6b51baee
4 changed files with 49 additions and 0 deletions
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11
src/mainboard/google/kahlee/mainboard.c
View File

@ -23,6 +23,7 @@
#include <boardid.h>
#include <soc/nvs.h>
#include <soc/smi.h>
#include <soc/southbridge.h>
#include <variant/ec.h>
#include <variant/thermal.h>
#include <vendorcode/google/chromeos/chromeos.h>
@ -125,6 +126,16 @@ static void mainboard_final(void *chip_info)
}
}
int mainboard_get_xhci_oc_map(uint16_t *map)
{
return variant_get_xhci_oc_map(map);
}
int mainboard_get_ehci_oc_map(uint16_t *map)
{
return variant_get_ehci_oc_map(map);
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = kahlee_enable,

18
src/mainboard/google/kahlee/variants/baseboard/gpio.c
View File

@ -328,3 +328,21 @@ const __attribute__((weak)) struct sci_source *get_gpe_table(size_t *num)
*num = ARRAY_SIZE(gpe_table);
return gpe_table;
}
int __attribute__((weak)) variant_get_xhci_oc_map(uint16_t *map)
{
*map = USB_OC0 << OC_PORT0_SHIFT; /* USB-C Port0 = OC0 */
*map |= USB_OC1 << OC_PORT1_SHIFT; /* USB-C Port1 = OC1 */
*map |= USB_OC_DISABLE << OC_PORT2_SHIFT;
*map |= USB_OC_DISABLE << OC_PORT3_SHIFT;
return 0;
}
int __attribute__((weak)) variant_get_ehci_oc_map(uint16_t *map)
{
*map = USB_OC2 << OC_PORT0_SHIFT; /* USB-A Port0 = OC2 */
*map |= USB_OC3 << OC_PORT1_SHIFT; /* USB-A Port1 = OC3 */
*map |= USB_OC_DISABLE << OC_PORT2_SHIFT;
*map |= USB_OC_DISABLE << OC_PORT3_SHIFT;
return 0;
}

2
src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
View File

@ -25,5 +25,7 @@ const GPIO_CONTROL *get_gpio_table(void);
const struct sci_source *get_gpe_table(size_t *num);
uint8_t variant_memory_sku(void);
int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len);
int variant_get_xhci_oc_map(uint16_t *usb_oc_map);
int variant_get_ehci_oc_map(uint16_t *usb_oc_map);
#endif /* __BASEBOARD_VARIANTS_H__ */

18
src/mainboard/google/kahlee/variants/kahlee/gpio.c
View File

@ -148,3 +148,21 @@ const struct sci_source *get_gpe_table(size_t *num)
*num = ARRAY_SIZE(gpe_table);
return gpe_table;
}
int variant_get_xhci_oc_map(uint16_t *map)
{
*map = USB_OC0 << OC_PORT0_SHIFT; /* USB-C Port0 = OC0 */
*map |= USB_OC1 << OC_PORT1_SHIFT; /* USB-C Port1 = OC1 */
*map |= USB_OC_DISABLE << OC_PORT2_SHIFT;
*map |= USB_OC_DISABLE << OC_PORT3_SHIFT;
return 0;
}
int variant_get_ehci_oc_map(uint16_t *map)
{
*map = USB_OC2 << OC_PORT0_SHIFT; /* USB-A Port0 = OC2 */
*map |= USB_OC_DISABLE << OC_PORT1_SHIFT;
*map |= USB_OC_DISABLE << OC_PORT2_SHIFT;
*map |= USB_OC_DISABLE << OC_PORT3_SHIFT;
return 0;
}