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mb/google/brask/var/kuldax: correct Type-A USB3 port0/1 tx_de_emp 

1. Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX
   signal integrity issue.
2. Disable unused USB port.

BUG=b:238230292
TEST=build FW and check Type-A USB3 port0/port1 RX pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8356ca30a965e5774a1556c5cb81e1586c55496c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
David Wu 2022-07-25 11:09:19 +08:00 committed by Felix Held
parent 234e37099a
commit df721bd0c3
1 changed files with 17 additions and 0 deletions
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17
src/mainboard/google/brya/variants/kuldax/overridetree.cb
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@ -6,6 +6,23 @@ fw_config
end
chip soc/intel/alderlake
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2 Port 2
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
register "usb3_ports[0]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_de_emp = 0x2B,
.tx_downscale_amp = 0x00,
}" # Type-A port A0
register "usb3_ports[1]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_de_emp = 0x2B,
.tx_downscale_amp = 0x00,
}" # Type-A port A1
register "serial_io_gspi_mode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,