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soc/intel/apollolake: Correct the gpio bank irq 

The gpio bank irq is not correct and hence gpio
bank handler is never called in case of gpio based irq.
Correct the gpio bank irq to enable gpio based irq.

BUG=chrome-os-partner:55433
TEST=cat /proc/interrupts | grep INT3452 should
output 14.

Change-Id: I54253786425b7d4c2007043d49a91dfa6db0397b
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15756
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Jagadish Krishnamoorthy 2016-07-19 16:25:12 -07:00 committed by Martin Roth
parent cc19806ae7
commit df7ad44853
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/apollolake/acpi/soc_int.asl
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@ -24,7 +24,7 @@
#define UART2_INT 6 /* Need to be shared by PMC and SCC only*/
#define UART3_INT 7 /* Need to be shared by PMC and SCC only*/
#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/
#define GPIO_BANK_INT 16
#define GPIO_BANK_INT 14
#define NPK_INT 16
#define PIRQA_INT 16
#define PIRQB_INT 17