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AGESA: Move romstage main entry under cpu 

As we now apply asmlinkage attributes to romstage_main()
entry, also x86_64 passes parameters on the stack.

Change-Id: If9938dbbe9a164c9c1029431499b51ffccb459c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18624
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-11-25 12:02:00 +02:00
parent 13cf135871
commit df7ff31c59
11 changed files with 158 additions and 265 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/cpu/amd/agesa/Makefile.inc
View File

@ -27,6 +27,7 @@ ifeq ($(CONFIG_AGESA_LEGACY), y)
cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram_legacy.inc
else
cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
romstage-y += romstage.c
endif
romstage-y += heapmanager.c

37
src/cpu/amd/agesa/cache_as_ram.inc
View File

@ -29,7 +29,6 @@
/*
* XMM map:
* xmm0: BIST
* xmm1: backup ebx -- cpu_init_detected
*/
.code32
@ -46,19 +45,9 @@ cache_as_ram_setup:
orl $(3<<9), %eax
movl %eax, %cr4
/* Get the cpu_init_detected */
mov $1, %eax
cpuid
shr $24, %ebx
/* Save the BIST result */
cvtsi2sd %ebp, %xmm0
/* for normal part %ebx already contain cpu_init_detected from fallback call */
/* Save the cpu_init_detected */
cvtsi2sd %ebx, %xmm1
post_code(0xa1)
AMD_ENABLE_STACK
@ -109,36 +98,19 @@ cache_as_ram_setup:
ljmp $0x18, $1f
1:
.code64
call early_all_cores
/* Pass the cpu_init_detected */
cvtsd2si %xmm1, %esi
/* Pass the BIST result */
cvtsd2si %xmm0, %edi
call cache_as_ram_main
.code32
#else
#endif
call early_all_cores
/* Restore the BIST result */
cvtsd2si %xmm0, %edx
/* Restore the cpu_init_detected */
cvtsd2si %xmm1, %ebx
/* Must maintain 16-byte stack alignment here. */
pushl $0x0
pushl $0x0
pushl %ebx /* init detected */
pushl $0x0
pushl %edx /* bist */
call cache_as_ram_main
#endif
call romstage_main
/* Should never see this postcode */
post_code(0xaf)
@ -170,6 +142,3 @@ disable_cache_as_ram:
ret
cache_as_ram_setup_out:
#ifdef __x86_64__
.code64
#endif

51
src/cpu/amd/agesa/family12/romstage.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2017 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -13,26 +14,17 @@
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/bist.h>
#include <superio/smsc/kbc1100/kbc1100.h>
#include <cpu/x86/lapic.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include "sb_cimx.h"
#include "SbPlatform.h"
#include <arch/cpu.h>
#include "platform_cfg.h"
void asmlinkage early_all_cores(void)
@ -40,36 +32,17 @@ void asmlinkage early_all_cores(void)
amd_initmmio();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void platform_once(struct sysinfo *cb)
{
struct sysinfo *cb = NULL;
u32 val;
gpioEarlyInit();
post_code(0x35);
sb_poweron_init();
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
gpioEarlyInit();
sb_poweron_init();
post_code(0x31);
board_BeforeAgesa(cb);
post_code(0x32);
post_code(0x33);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
// Load MPB
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
board_BeforeAgesa(cb);
}
void agesa_main(struct sysinfo *cb)
{
post_code(0x36);
agesawrapper_amdinitreset();

61
src/cpu/amd/agesa/family14/romstage.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2017 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -13,30 +14,16 @@
* GNU General Public License for more details.
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <stdint.h>
#include <string.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/mtrr.h>
#include <console/console.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <sb_cimx.h>
void asmlinkage early_all_cores(void)
@ -44,40 +31,22 @@ void asmlinkage early_all_cores(void)
amd_initmmio();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void platform_once(struct sysinfo *cb)
{
struct sysinfo *cb = NULL;
u32 val;
sb_Poweron_Init();
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
post_code(0x31);
board_BeforeAgesa(cb);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
board_BeforeAgesa(cb);
}
void agesa_main(struct sysinfo *cb)
{
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x39);
agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
if (!cb->s3resume) {
printk(BIOS_INFO, "Normal boot\n");
post_code(0x40);
@ -107,5 +76,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x50);
copy_and_run();
/* Not reached */
}

49
src/cpu/amd/agesa/family15/romstage.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2017 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -15,17 +16,16 @@
#include <lib.h>
#include <reset.h>
#include <stdint.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <arch/stages.h>
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h"
#include <cpu/amd/agesa/s3_resume.h>
#include <console/console.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h>
#include <sb_cimx.h>
@ -35,39 +35,26 @@ void asmlinkage early_all_cores(void)
amd_initmmio();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void platform_once(struct sysinfo *cb)
{
struct sysinfo *cb = NULL;
u32 val;
/*
* SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
* Disable all Pcie Bridges to work around It.
*/
sr56x0_rd890_disable_pcie_bridge();
post_code(0x31);
nb_Poweron_Init();
/* Halt if there was a built in self test failure */
post_code(0x33);
report_bist_failure(bist);
sb_Poweron_Init();
board_BeforeAgesa(cb);
console_init();
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
}
void agesa_main(struct sysinfo *cb)
{
post_code(0x37);
agesawrapper_amdinitreset();
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x38);
/*
* SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
* Disable all Pcie Bridges to work around It.
*/
sr56x0_rd890_disable_pcie_bridge();
post_code(0x39);
nb_Poweron_Init();
post_code(0x3A);
sb_Poweron_Init();
}
post_code(0x3B);
agesawrapper_amdinitearly();
@ -97,4 +84,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x51);
copy_and_run();
/* Not reached */
}

53
src/cpu/amd/agesa/family15rl/romstage.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2017 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -13,61 +14,35 @@
* GNU General Public License for more details.
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <cpu/amd/car.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <stdint.h>
#include <string.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
void asmlinkage early_all_cores(void)
{
amd_initmmio();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void platform_once(struct sysinfo *cb)
{
struct sysinfo *cb = NULL;
u32 val;
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
board_BeforeAgesa(cb);
post_code(0x31);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
board_BeforeAgesa(cb);
}
void agesa_main(struct sysinfo *cb)
{
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x39);
agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
if (!cb->s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
@ -90,5 +65,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x50);
copy_and_run();
/* Not reached */
}

56
src/cpu/amd/agesa/family15tn/romstage.c
View File

@ -3,6 +3,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2017 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -14,63 +15,36 @@
* GNU General Public License for more details.
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <cpu/amd/car.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <stdint.h>
#include <string.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
void asmlinkage early_all_cores(void)
{
amd_initmmio();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void platform_once(struct sysinfo *cb)
{
struct sysinfo *cb = NULL;
u32 val;
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
post_code(0x31);
board_BeforeAgesa(cb);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
board_BeforeAgesa(cb);
}
void agesa_main(struct sysinfo *cb)
{
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x39);
agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
if (!cb->s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
@ -93,4 +67,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x50);
copy_and_run();
/* Not reached */
}

54
src/cpu/amd/agesa/family16kb/romstage.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2017 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -13,62 +14,35 @@
* GNU General Public License for more details.
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <cpu/amd/car.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <stdint.h>
#include <string.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
void asmlinkage early_all_cores(void)
{
amd_initmmio();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void platform_once(struct sysinfo *cb)
{
struct sysinfo *cb = NULL;
u32 val;
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
board_BeforeAgesa(cb);
post_code(0x31);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
board_BeforeAgesa(cb);
}
void agesa_main(struct sysinfo *cb)
{
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x39);
agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
if (!cb->s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
@ -92,5 +66,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x50);
copy_and_run();
/* Not reached */
}

56
src/cpu/amd/agesa/romstage.c Normal file
View File

@ -0,0 +1,56 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <cpu/amd/car.h>
#include <cpu/x86/bist.h>
#include <console/console.h>
#include <smp/node.h>
#include <string.h>
#include <northbridge/amd/agesa/state_machine.h>
static void fill_sysinfo(struct sysinfo *cb)
{
memset(cb, 0, sizeof(*cb));
cb->s3resume = acpi_is_wakeup_s3();
}
void * asmlinkage romstage_main(unsigned long bist)
{
struct sysinfo romstage_state;
struct sysinfo *cb = &romstage_state;
u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24);
fill_sysinfo(cb);
if ((initial_apic_id == 0) && boot_cpu()) {
platform_once(cb);
console_init();
}
printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n",
initial_apic_id, cpuid_eax(1));
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
agesa_main(cb);
/* Not reached */
return NULL;
}

2
src/include/cpu/amd/car.h
View File

@ -18,4 +18,6 @@ void disable_cache_as_ram(void);
void asmlinkage early_all_cores(void);
void * asmlinkage romstage_main(unsigned long bist);
#endif

3
src/northbridge/amd/agesa/state_machine.h
View File

@ -25,4 +25,7 @@ struct sysinfo
void board_BeforeAgesa(struct sysinfo *cb);
void platform_once(struct sysinfo *cb);
void agesa_main(struct sysinfo *cb);
#endif /* _STATE_MACHINE_H_ */