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soc/intel/skylake/pmutil: Correct soc_smi_sts_array() 

The array was copied from Broadwell, which uses a different bit layout
for SMI_STS. Copy the array from Cannonlake instead, because Skylake
uses the same bit layout. This could be deduplicated in the future.

Change-Id: I1c4df727c549eac6f361754d6011bf302da64c5a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50929
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-02-19 16:35:45 +01:00 committed by Patrick Georgi
parent 560eab7de5
commit df8462c36a
1 changed files with 19 additions and 21 deletions
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40
src/soc/intel/skylake/pmutil.c
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@ -33,27 +33,25 @@
const char *const *soc_smi_sts_array(size_t *smi_arr) const char *const *soc_smi_sts_array(size_t *smi_arr)
{ {
static const char *const smi_sts_bits[] = { static const char *const smi_sts_bits[] = {
[2] = "BIOS", [BIOS_STS_BIT] = "BIOS",
[3] = "LEGACY_USB", [LEGACY_USB_STS_BIT] = "LEGACY_USB",
[4] = "SLP_SMI", [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
[5] = "APM", [APM_STS_BIT] = "APM",
[6] = "SWSMI_TMR", [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
[8] = "PM1", [PM1_STS_BIT] = "PM1",
[9] = "GPE0", [GPE0_STS_BIT] = "GPE0",
[10] = "GPI", [GPIO_STS_BIT] = "GPI",
[11] = "MCSMI", [MCSMI_STS_BIT] = "MCSMI",
[12] = "DEVMON", [DEVMON_STS_BIT] = "DEVMON",
[13] = "TCO", [TCO_STS_BIT] = "TCO",
[14] = "PERIODIC", [PERIODIC_STS_BIT] = "PERIODIC",
[15] = "SERIRQ_SMI", [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
[16] = "SMBUS_SMI", [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
[17] = "LEGACY_USB2", [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
[18] = "INTEL_USB2", [MONITOR_STS_BIT] = "MONITOR",
[20] = "PCI_EXP_SMI", [SPI_SMI_STS_BIT] = "SPI",
[21] = "MONITOR", [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
[26] = "SPI", [ESPI_SMI_STS_BIT] = "ESPI_SMI",
[27] = "GPIO_UNLOCK",
[28] = "ESPI_SMI",
}; };
*smi_arr = ARRAY_SIZE(smi_sts_bits); *smi_arr = ARRAY_SIZE(smi_sts_bits);