soc/intel/skylake/pmutil: Correct soc_smi_sts_array()

The array was copied from Broadwell, which uses a different bit layout
for SMI_STS. Copy the array from Cannonlake instead, because Skylake
uses the same bit layout. This could be deduplicated in the future.

Change-Id: I1c4df727c549eac6f361754d6011bf302da64c5a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50929
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/skylake/pmutil.c

@@ -33,27 +33,25 @@
 const char *const *soc_smi_sts_array(size_t *smi_arr)
 {
 	static const char *const smi_sts_bits[] = {
-		[2] = "BIOS",
-		[3] = "LEGACY_USB",
-		[4] = "SLP_SMI",
-		[5] = "APM",
-		[6] = "SWSMI_TMR",
-		[8] = "PM1",
-		[9] = "GPE0",
-		[10] = "GPI",
-		[11] = "MCSMI",
-		[12] = "DEVMON",
-		[13] = "TCO",
-		[14] = "PERIODIC",
-		[15] = "SERIRQ_SMI",
-		[16] = "SMBUS_SMI",
-		[17] = "LEGACY_USB2",
-		[18] = "INTEL_USB2",
-		[20] = "PCI_EXP_SMI",
-		[21] = "MONITOR",
-		[26] = "SPI",
-		[27] = "GPIO_UNLOCK",
-		[28] = "ESPI_SMI",
+		[BIOS_STS_BIT] = "BIOS",
+		[LEGACY_USB_STS_BIT] = "LEGACY_USB",
+		[SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
+		[APM_STS_BIT] = "APM",
+		[SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
+		[PM1_STS_BIT] = "PM1",
+		[GPE0_STS_BIT] = "GPE0",
+		[GPIO_STS_BIT] = "GPI",
+		[MCSMI_STS_BIT] = "MCSMI",
+		[DEVMON_STS_BIT] = "DEVMON",
+		[TCO_STS_BIT] = "TCO",
+		[PERIODIC_STS_BIT] = "PERIODIC",
+		[SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
+		[SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
+		[PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
+		[MONITOR_STS_BIT] = "MONITOR",
+		[SPI_SMI_STS_BIT] = "SPI",
+		[GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
+		[ESPI_SMI_STS_BIT] = "ESPI_SMI",
 	};
 
 	*smi_arr = ARRAY_SIZE(smi_sts_bits);