src/mainboard/asrock/e350m1: Properly indent devicetree.cb
Trivial: clean up spaces to tabs to properly indent devicetree.cb Change-Id: Id5577139cfa039898af3b2158fdd6869ac9d2ec1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5612 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
parent
178a60b4b3
commit
dfa8a32f1f
|
@ -17,43 +17,44 @@
|
|||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
chip northbridge/amd/agesa/family14/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/agesa/family14
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1510 inherit
|
||||
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
|
||||
# device pci 18.0 on # northbridge
|
||||
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
|
||||
device pci 1.1 on end # Internal HDMI Audio
|
||||
device pci 4.0 on end # PCIE P2P bridge 0x9604
|
||||
device pci 5.0 off end # PCIE P2P bridge 0x9605
|
||||
device pci 6.0 off end # PCIE P2P bridge 0x9606
|
||||
device pci 7.0 off end # PCIE P2P bridge 0x9607
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
end # agesa northbridge
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/agesa/family14
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1510 inherit
|
||||
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
|
||||
# device pci 18.0 on # northbridge
|
||||
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
|
||||
|
||||
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x439d
|
||||
device pci 1.1 on end # Internal HDMI Audio
|
||||
device pci 4.0 on end # PCIE P2P bridge 0x9604
|
||||
device pci 5.0 off end # PCIE P2P bridge 0x9605
|
||||
device pci 6.0 off end # PCIE P2P bridge 0x9606
|
||||
device pci 7.0 off end # PCIE P2P bridge 0x9607
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
end # agesa northbridge
|
||||
|
||||
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x439d
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
|
@ -96,7 +97,7 @@ chip northbridge/amd/agesa/family14/root_complex
|
|||
end
|
||||
end #LPC
|
||||
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
|
||||
device pci 14.5 on end # USB 2
|
||||
device pci 14.5 on end # USB 2
|
||||
device pci 15.0 on end # PCIe PortA
|
||||
device pci 15.1 on end # PCIe PortB: NIC
|
||||
device pci 15.2 on end # PCIe PortC: USB3
|
||||
|
@ -112,19 +113,19 @@ chip northbridge/amd/agesa/family14/root_complex
|
|||
#0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3.
|
||||
register "gpp_configuration" = "4"
|
||||
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
end #southbridge/amd/cimx/sb800
|
||||
# end # device pci 18.0
|
||||
# end # device pci 18.0
|
||||
#
|
||||
# These seem unnecessary
|
||||
device pci 18.0 on end
|
||||
#device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
device pci 18.6 on end
|
||||
device pci 18.7 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
device pci 18.6 on end
|
||||
device pci 18.7 on end
|
||||
|
||||
register "spdAddrLookup" = "
|
||||
{
|
||||
|
@ -132,7 +133,6 @@ chip northbridge/amd/agesa/family14/root_complex
|
|||
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
|
||||
}"
|
||||
|
||||
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
|
||||
end #domain
|
||||
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
|
||||
end #domain
|
||||
end #northbridge/amd/agesa/family14/root_complex
|
||||
|
||||
|
|
Loading…
Reference in New Issue