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asrock/e350m1: disable unconnected GPP PCIe clocks

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connections checked by desoldering the FCH and looking at the PCB

this lowers the power consumption by about 150-200mW measured on primary side

based on change #5397

Change-Id: I986c4cc73a247994f2a47fdfd03f585069ca9385
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/11866
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Felix Held 2015-10-11 13:24:40 +02:00 committed by David Hendricks
parent 354c11d10e
commit dfb53ef0a5
1 changed files with 15 additions and 0 deletions
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15
src/mainboard/asrock/e350m1/mainboard.c
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@ -25,6 +25,7 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <southbridge/amd/cimx/cimx_util.h>
#include "SBPLATFORM.h"
//#define SMBUS_IO_BASE 0x6000
void set_pcie_reset(void);
@ -54,6 +55,20 @@ static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
/* Power off unused clock pins of GPP PCIe devices */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
/*
* GPP CLK0 connected to unpopulated mini PCIe slot
* GPP CLK1 connected to ethernet chip
*/
write8(misc_mem_clk_cntrl + 0, 0xFF);
/* GPP CLK2 connected to the external USB3 controller */
write8(misc_mem_clk_cntrl + 1, 0x0F);
write8(misc_mem_clk_cntrl + 2, 0x00);
write8(misc_mem_clk_cntrl + 3, 0x00);
/* SLT_GFX_CLK connected to PCIe slot */
write8(misc_mem_clk_cntrl + 4, 0xF0);
/*
* Initialize ASF registers to an arbitrary address because someone
* long ago set things up this way inside the SPD read code. The