mb/intel/coffeelake_rvp: Add support for new board coffeelake RVP
Add support for new board coffeelake RVP. This patch is a copy patch and copies entire coffeelake_rvp folder from cannonlake_rvp. Changes done on top of copy: 1. Change copyright year from 2017 to 2018 2. Rename Cannonlake to Coffelake whenever applicable 3. Update entries in Kconfig and Kconfig.name 4. Rename variant directories to match coffeelake boards Change-Id: Id37bfeb0ae51fd630fec96273216dbb2900782c7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27904 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maulik V Vaghela
Patrick Georgi
parent
8bd25abc05
commit
dfc9917080
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@ -0,0 +1,67 @@
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if BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_COFFEELAKE_RVP11
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select GENERIC_SPD_BIN
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select MAINBOARD_HAS_CHROMEOS
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select GENERIC_SPD_BIN
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_GENERIC
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select SOC_INTEL_COFFEELAKE
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config MAINBOARD_DIR
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string
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default "intel/coffeelake_rvp"
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config VARIANT_DIR
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string
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default "cfl_u" if BOARD_INTEL_COFFEELAKE_RVPU
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default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11
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config MAINBOARD_PART_NUMBER
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string
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default "Coffeelake RVP"
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config MAINBOARD_VENDOR
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string
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default "Intel"
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config MAINBOARD_FAMILY
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string
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default "Intel_coffeelake_rvp"
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config MAX_CPUS
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int
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default 8
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config DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config INCLUDE_SND_MAX98357_DA7219_NHLT
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bool "Include blobs for audio with MAX98357_DA7219"
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select DRIVERS_GENERIC_MAX98357A
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select DRIVERS_I2C_DA7219
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select NHLT_DMIC_4CH_16B
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select NHLT_DMIC_2CH_16B
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select NHLT_DA7219
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select NHLT_MAX98357
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config INCLUDE_SND_MAX98373_NHLT
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bool "Include blobs for audio with MAX98373"
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select DRIVERS_I2C_MAX98373
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select NHLT_DMIC_4CH_16B
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select NHLT_DMIC_2CH_16B
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select NHLT_MAX98373
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config DIMM_SPD_SIZE
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int
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default 512
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config VBOOT
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select VBOOT_LID_SWITCH
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select VBOOT_MOCK_SECDATA
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endif
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@ -0,0 +1,6 @@
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comment "Coffeelake RVP"
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config BOARD_INTEL_COFFEELAKE_RVPU
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bool "-> Coffeelake U LPDDR4 RVP"
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config BOARD_INTEL_COFFEELAKE_RVP11
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bool "-> Coffeelake H LPDDR4 RVP11"
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@ -0,0 +1,33 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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## Copyright (C) 2018 Intel Corporation.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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subdirs-y += spd
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bootblock-y += bootblock.c
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bootblock-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += mainboard.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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@ -0,0 +1 @@
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/* Nothing here */
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@ -0,0 +1,6 @@
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Vendor name: Intel
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Board name: Coffeelake rvp
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Category: eval
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,28 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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void bootblock_mainboard_init(void)
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{
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const struct pad_config *pads;
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size_t num;
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pads = variant_early_gpio_table(&num);
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gpio_configure_pads(pads, num);
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}
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@ -0,0 +1,64 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <baseboard/variants.h>
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#include <gpio.h>
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#include <rules.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#if ENV_RAMSTAGE
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#include <boot/coreboot_tables.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
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{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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#endif /* ENV_RAMSTAGE */
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int get_lid_switch(void)
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{
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/* Lid always open */
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return 1;
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}
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int get_recovery_mode_switch(void)
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{
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return 0;
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}
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int get_write_protect_state(void)
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{
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/* No write protect */
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return 0;
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}
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void mainboard_chromeos_acpi_generate(void)
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{
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const struct cros_gpio *gpios;
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size_t num;
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gpios = variant_cros_gpios(&num);
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chromeos_acpi_gpio_generate(gpios, num);
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}
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@ -0,0 +1,44 @@
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FLASH@0xff000000 0x1000000 {
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SI_ALL@0x0 0x380000 {
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SI_DESC@0x0 0x1000
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SI_EC@0x01000 0x80000
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SI_ME@0x81000 0x2ff000
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}
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SI_BIOS@0x380000 0xc80000 {
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RW_SECTION_A@0x0 0x368000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x357fc0
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RW_FWID_A@0x367fc0 0x40
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}
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RW_SECTION_B@0x368000 0x368000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x357fc0
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RW_FWID_B@0x367fc0 0x40
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}
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RW_MISC@0x6d0000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x20000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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}
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RW_ELOG@0x20000 0x4000
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RW_SHARED@0x24000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD@0x28000 0x2000
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RW_NVRAM@0x2a000 0x6000
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}
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RW_LEGACY(CBFS)@0x700000 0x200000
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WP_RO@0x900000 0x380000 {
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RO_VPD@0x0 0x4000
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RO_UNUSED@0x4000 0xc000
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RO_SECTION@0x10000 0x370000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0xef000
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COREBOOT(CBFS)@0xf0000 0x280000
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}
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}
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}
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}
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@ -0,0 +1,49 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2018 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x05, // DSDT revision: ACPI v5.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20110725 // OEM revision
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)
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{
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// Some generic macros
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#include <soc/intel/cannonlake/acpi/platform.asl>
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// global NVS and variables
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#include <soc/intel/cannonlake/acpi/globalnvs.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/cannonlake/acpi/northbridge.asl>
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#include <soc/intel/cannonlake/acpi/southbridge.asl>
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}
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}
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#if IS_ENABLED(CONFIG_CHROMEOS)
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// Chrome OS specific
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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#endif
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// Chipset specific sleep states
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#include <soc/intel/cannonlake/acpi/sleepstates.asl>
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}
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@ -0,0 +1,68 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <baseboard/variants.h>
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#include <device/device.h>
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#include <nhlt.h>
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#include <soc/gpio.h>
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#include <soc/nhlt.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <variant/gpio.h>
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static void mainboard_init(void *chip_info)
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{
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const struct pad_config *pads;
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size_t num;
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pads = variant_gpio_table(&num);
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gpio_configure_pads(pads, num);
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}
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static unsigned long mainboard_write_acpi_tables(struct device *device,
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unsigned long current,
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acpi_rsdp_t *rsdp)
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{
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uintptr_t start_addr;
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uintptr_t end_addr;
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struct nhlt *nhlt;
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start_addr = current;
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nhlt = nhlt_init();
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if (nhlt == NULL)
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return start_addr;
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variant_nhlt_init(nhlt);
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end_addr = nhlt_soc_serialize(nhlt, start_addr);
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if (end_addr != start_addr)
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acpi_add_table(rsdp, (void *)start_addr);
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return end_addr;
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
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dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.enable_dev = mainboard_enable,
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};
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@ -0,0 +1,54 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Google Inc.
|
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* Copyright (C) 2018 Intel Corp.
|
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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#include <arch/byteorder.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <fsp/api.h>
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#include <soc/romstage.h>
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#include "spd/spd.h"
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#include <string.h>
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#include <spd_bin.h>
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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FSP_M_CONFIG *mem_cfg;
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mem_cfg = &mupd->FspmConfig;
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u8 spd_index;
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mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0);
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mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1);
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mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0);
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mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1);
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mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
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mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
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mem_cfg->DqPinsInterleaved = 0;
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mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
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mem_cfg->ECT = 1; /* Early Command Training Enabled */
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spd_index = 2;
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struct region_device spd_rdev;
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if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
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die("spd.bin not found\n");
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mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
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/* Memory leak is ok since we have memory mapped boot media */
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mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
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mem_cfg->RefClk = 0; /* Auto Select CLK freq */
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mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
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}
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@ -0,0 +1,28 @@
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##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2014 Google Inc.
|
||||
## Copyright (C) 2018 Intel Corporation.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
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romstage-y += spd_util.c
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SPD_BIN = $(obj)/spd.bin
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SPD_SOURCES = empty # 0b000
|
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SPD_SOURCES += samsung_ddr4_4GB # 0b001 Dual Channel 4GB
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SPD_SOURCES += samsung_lpddr4_8GB # 0b001 Dual Channel 8GB
|
||||
SPD_SOURCES += empty # 0b011
|
||||
SPD_SOURCES += empty # 0b100
|
||||
SPD_SOURCES += empty # 0b101
|
||||
SPD_SOURCES += empty # 0b110
|
||||
SPD_SOURCES += empty # 0b111
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
23 11 0C 03 84 19 00 08 00 60 00 03 01 03 00 00
|
||||
00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E 20 08
|
||||
00 05 70 03 00 A8 18 28 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04
|
||||
16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 64 20
|
||||
0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 CE 01 16 26 02 FC 5D BE 4D 34 37 31 41 35 31
|
||||
34 33 45 42 31 2D 43 54 44 20 20 20 20 00 80 CE
|
||||
00 33 30 32 4A 30 30 30 23 00 01 00 00 00 00 00
|
||||
01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
23 10 10 0E 15 19 95 08 00 40 00 00 0A 22 00 00
|
||||
48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0
|
||||
02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
|
||||
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2018 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_SPD_H
|
||||
#define MAINBOARD_SPD_H
|
||||
|
||||
#define RCOMP_TARGET_PARAMS 0x5
|
||||
|
||||
void mainboard_fill_dq_map_ch0(void *dq_map_ptr);
|
||||
void mainboard_fill_dq_map_ch1(void *dq_map_ptr);
|
||||
void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr);
|
||||
void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr);
|
||||
void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
|
||||
void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <arch/byteorder.h>
|
||||
#include <cbfs.h>
|
||||
#include <console/console.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include "spd.h"
|
||||
|
||||
void mainboard_fill_dq_map_ch0(void *dq_map_ptr)
|
||||
{
|
||||
/* DQ byte map Ch0 */
|
||||
const u8 dq_map[12] = {
|
||||
0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
|
||||
|
||||
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
|
||||
}
|
||||
|
||||
void mainboard_fill_dq_map_ch1(void *dq_map_ptr)
|
||||
{
|
||||
const u8 dq_map[12] = {
|
||||
0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
|
||||
|
||||
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
|
||||
}
|
||||
|
||||
void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)
|
||||
{
|
||||
/* DQS CPU<>DRAM map Ch0 */
|
||||
const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };
|
||||
|
||||
const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };
|
||||
|
||||
if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU))
|
||||
memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
|
||||
else
|
||||
memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
|
||||
}
|
||||
|
||||
void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)
|
||||
{
|
||||
/* DQS CPU<>DRAM map Ch1 */
|
||||
const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };
|
||||
|
||||
const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };
|
||||
|
||||
if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU))
|
||||
memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
|
||||
else
|
||||
memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
|
||||
}
|
||||
|
||||
void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
|
||||
{
|
||||
/* Rcomp resistor */
|
||||
const u16 RcompResistor[3] = { 100, 100, 100 };
|
||||
memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
|
||||
}
|
||||
|
||||
void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
|
||||
{
|
||||
/* Rcomp target */
|
||||
static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
|
||||
80, 40, 40, 40, 30 };
|
||||
|
||||
memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
|
||||
}
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
bootblock-y += gpio.c
|
||||
|
||||
ramstage-y += gpio.c
|
||||
ramstage-y += nhlt.c
|
||||
|
|
@ -0,0 +1,322 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
#include <compiler.h>
|
||||
|
||||
/* Pad configuration in ramstage*/
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* GPPC */
|
||||
/* A0 : RCINB_TIME_SYNC_1 */
|
||||
/* A1 : ESPI_IO_0 */
|
||||
/* A2 : ESPI_IO_1 */
|
||||
/* A3 : ESPI_IO_2 */
|
||||
/* A4 : ESPI_IO_3 */
|
||||
/* A5 : ESPI_CSB */
|
||||
/* A6 : SERIRQ */
|
||||
/* A7 : PRIQAB_GSP10_CS1B */
|
||||
PAD_CFG_GPI_SCI_HIGH(GPP_A7, UP_20K, DEEP, EDGE_SINGLE),
|
||||
/* A8 : CLKRUNB */
|
||||
PAD_CFG_GPO(GPP_A8, 1, PLTRST),
|
||||
/* A9 : CLKOUT_LPC_0_ESPI_CLK */
|
||||
/* A10 : CLKOUT_LPC_1 */
|
||||
/* A11 : PMEB_GSP11_CS1B */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_A11, UP_20K, DEEP, LEVEL),
|
||||
/* A12 : BM_BUSYB_ISH__GP_6 */
|
||||
/* A13 : SUSWARNB_SUSPWRDNACK */
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
/* A14 : SUS_STATB_ESPI_RESETB */
|
||||
/* A15 : SUSACKB */
|
||||
PAD_CFG_GPO(GPP_A15, 1, PLTRST),
|
||||
/* A16 : SD_1P8_SEL */
|
||||
PAD_CFG_GPO(GPP_A16, 0, PLTRST),
|
||||
/* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */
|
||||
/* A18 : ISH_GP_0 */
|
||||
PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1),
|
||||
/* A19 : ISH_GP_1 */
|
||||
PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1),
|
||||
/* A20 : aduio codec irq */
|
||||
PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP),
|
||||
/* A21 : ISH_GP_3 */
|
||||
PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1),
|
||||
/* A22 : ISH_GP_4 */
|
||||
PAD_CFG_NF(GPP_A22, UP_20K, DEEP, NF1),
|
||||
/* A23 : ISH_GP_5 */
|
||||
PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1),
|
||||
|
||||
/* B0 : CORE_VID_0 */
|
||||
/* B1 : CORE_VID_1 */
|
||||
/* B2 : VRALERTB */
|
||||
PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP, LEVEL, NONE),
|
||||
/* B3 : CPU_GP_2 */
|
||||
PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, LEVEL, NONE),
|
||||
/* B4 : CPU_GP_3 */
|
||||
PAD_CFG_GPO(GPP_B4, 1, DEEP),
|
||||
/* B5 : SRCCLKREQB_0 */
|
||||
/* B6 : SRCCLKREQB_1 */
|
||||
/* B7 : SRCCLKREQB_2 */
|
||||
/* B8 : SRCCLKREQB_3 */
|
||||
/* B9 : SRCCLKREQB_4 */
|
||||
/* B10 : SRCCLKREQB_5 */
|
||||
/* B11 : EXT_PWR_GATEB */
|
||||
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
|
||||
/* B12 : SLP_S0B */
|
||||
/* B13 : PLTRSTB */
|
||||
/* B14 : SPKR */
|
||||
PAD_CFG_GPO(GPP_B14, 1, PLTRST),
|
||||
/* B15 : GSPI0_CS0B */
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
/* B16 : GSPI0_CLK */
|
||||
PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE),
|
||||
/* B17 : GSPI0_MISO */
|
||||
PAD_CFG_GPO(GPP_B17, 1, PLTRST),
|
||||
/* B18 : GSPI0_MOSI */
|
||||
PAD_CFG_GPO(GPP_B18, 1, PLTRST),
|
||||
/* B19 : GSPI1_CS0B */
|
||||
/* B20 : GSPI1_CLK_NFC_CLK */
|
||||
/* B21 : GSPI1_MISO_NFC_CLKREQ */
|
||||
/* B22 : GSP1_MOSI */
|
||||
/* B23 : SML1ALERTB_PCHHOTB */
|
||||
PAD_CFG_GPO(GPP_B23, 1, DEEP),
|
||||
|
||||
/* C0 : SMBCLK */
|
||||
/* C1 : SMBDATA */
|
||||
/* C2 : SMBALERTB */
|
||||
PAD_CFG_GPO(GPP_C2, 1, DEEP),
|
||||
/* C3 : SML0CLK */
|
||||
/* C4 : SML0DATA */
|
||||
/* C5 : SML0ALERTB */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL),
|
||||
/* C6 : SML1CLK */
|
||||
/* C7 : SML1DATA */
|
||||
/* C8 : UART0_RXD */
|
||||
PAD_CFG_GPI_APIC(GPP_C8, UP_20K, DEEP, LEVEL, INVERT),
|
||||
/* C9 : UART0_TXD */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE),
|
||||
/* C10 : UART0_RTSB */
|
||||
PAD_CFG_GPO(GPP_C10, 0, PLTRST),
|
||||
/* C11 : UART0_CTSB */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_C11, UP_20K, DEEP, LEVEL),
|
||||
/* C12 : UART1_RXD_ISH_UART1_RXD */
|
||||
PAD_CFG_GPO(GPP_C12, 1, PLTRST),
|
||||
/* C13 : UART1_RXD_ISH_UART1_TXD */
|
||||
/* C14 : UART1_RXD_ISH_UART1_RTSB */
|
||||
/* C15 : UART1_RXD_ISH_UART1_CTSB */
|
||||
PAD_CFG_GPO(GPP_C15, 1, PLTRST),
|
||||
/* C16 : I2C0_SDA */
|
||||
/* C17 : I2C0_SCL */
|
||||
/* C18 : I2C1_SDA */
|
||||
/* C19 : I2C1_SCL */
|
||||
/* C20 : UART2_RXD */
|
||||
/* C21 : UART2_TXD */
|
||||
/* C22 : UART2_RTSB */
|
||||
/* C23 : UART2_CTSB */
|
||||
|
||||
/* D0 : SPI1_CSB_BK_0 */
|
||||
/* D1 : SPI1_CLK_BK_1 */
|
||||
/* D2 : SPI1_MISO_IO_1_BK_2 */
|
||||
/* D3 : SPI1_MOSI_IO_0_BK_3 */
|
||||
/* D4 : IMGCLKOUT_0_BK_4 */
|
||||
/* D5 : ISH_I2C0_SDA */
|
||||
/* D6 : ISH_I2C0_SCL */
|
||||
/* D7 : ISH_I2C1_SDA */
|
||||
/* D8 : ISH_I2C1_SCL */
|
||||
/* D9 : ISH_SPI_CSB */
|
||||
PAD_CFG_GPO(GPP_D9, 1, PLTRST),
|
||||
/* D10 : ISH_SPI_CLK */
|
||||
PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST, EDGE_SINGLE, NONE),
|
||||
/* D11 : ISH_SPI_MISO_GP_BSSB_CLK */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL),
|
||||
/* D12 : ISH_SPI_MOSI_GP_BSSB_DI */
|
||||
/* D13 : ISH_UART0_RXD_SML0BDATA */
|
||||
PAD_CFG_GPO(GPP_D13, 1, DEEP),
|
||||
/* D14 : ISH_UART0_TXD_SML0BCLK */
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
/* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */
|
||||
/* D16 : ISH_UART0_CTSB_SML0BALERTB */
|
||||
PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL),
|
||||
/* D17 : DMIC_CLK_1_SNDW3_CLK */
|
||||
PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),
|
||||
/* D18 : DMIC_DATA_1_SNDW3_DATA */
|
||||
PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),
|
||||
/* D19 : DMIC_CLK_0_SNDW4_CLK */
|
||||
PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),
|
||||
/* D20 : DMIC_DATA_0_SNDW4_DATA */
|
||||
PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),
|
||||
/* D21 : SPI1_IO_2 */
|
||||
PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1),
|
||||
/* D22 : SPI1_IO_3 */
|
||||
PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1),
|
||||
/* D23 : SPP_MCLK */
|
||||
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
|
||||
/* E0 : SATAXPCIE_0_SATAGP_0 */
|
||||
#if IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVP11)
|
||||
PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),
|
||||
#endif
|
||||
/* E1 : SATAXPCIE_1_SATAGP_1 */
|
||||
/* E2 : SATAXPCIE_2_SATAGP_2 */
|
||||
PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST),
|
||||
/* E3 : CPU_GP_0 */
|
||||
PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE),
|
||||
/* E4 : SATA_DEVSLP_0 */
|
||||
PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
|
||||
/* E5 : SATA_DEVSLP_1 */
|
||||
/* E6 : SATA_DEVSLP_2 */
|
||||
PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE),
|
||||
/* E7 : CPU_GP_1 */
|
||||
PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE),
|
||||
/* E8 : SATA_LEDB */
|
||||
/* E9 : USB2_OCB_0_GP_BSSB_CLK */
|
||||
/* E10 : USB2_OCB_1_GP_BSSB_DI */
|
||||
/* E11 : USB2_OCB_2 */
|
||||
/* E12 : USB2_OCB_3 */
|
||||
/* E13 : DDSP_HPD_0_DISP_MISC_0 */
|
||||
/* E14 : DDSP_HPD_0_DISP_MISC_1 */
|
||||
/* E15 : DDSP_HPD_0_DISP_MISC_2 */
|
||||
/* E16 : EMMC_EN */
|
||||
PAD_CFG_GPO(GPP_E16, 1, PLTRST),
|
||||
/* E17 : EDP_HPD_DISP_MISC_4 */
|
||||
/* E18 : DDPB_CTRLCLK */
|
||||
/* E19 : DDPB_CTRLDATA */
|
||||
/* E20 : DDPC_CTRLCLK */
|
||||
/* E21 : DDPC_CTRLDATA */
|
||||
/* E22 : DDPD_CTRLCLK */
|
||||
/* E23 : DDPD_CTRLDATA */
|
||||
|
||||
/* F0 : CNV_GNSS_PA_BLANKING */
|
||||
PAD_CFG_GPI(GPP_F0, NONE, PLTRST),
|
||||
/* F1 : CNV_GNSS_FAT */
|
||||
PAD_CFG_TERM_GPO(GPP_F1, 1, UP_20K, DEEP),
|
||||
/* F2 : CNV_GNSS_SYSCK */
|
||||
PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST),
|
||||
/* F3 : GPP_F_3 */
|
||||
PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST),
|
||||
/* F4 : CNV_BRI_DT_UART0_RTSB */
|
||||
/* F5 : CNV_BRI_RSP_UART0_RXD */
|
||||
/* F6 : CNV_RGI_DT_UART0_TXD */
|
||||
/* F7 : CNV_RGI_DT_RSP_UART9_CTSB */
|
||||
/* F8 : CNV_MFUART2_RXD */
|
||||
PAD_CFG_NF(GPP_F8, UP_20K, DEEP, NF1),
|
||||
/* F9 : CNV_MFUART2_TXD */
|
||||
PAD_CFG_NF(GPP_F9, UP_20K, DEEP, NF1),
|
||||
/* F10 : GPP_F_10 */
|
||||
PAD_CFG_GPO(GPP_F10, 1, PLTRST),
|
||||
/* F11 : EMMC_CMD */
|
||||
/* F12 : EMMC_DATA0 */
|
||||
/* F13 : EMMC_DATA1 */
|
||||
/* F14 : EMMC_DATA2 */
|
||||
/* F15 : EMMC_DATA3 */
|
||||
/* F16 : EMMC_DATA4 */
|
||||
/* F17 : EMMC_DATA5 */
|
||||
/* F18 : EMMC_DATA6 */
|
||||
/* F19 : EMMC_DATA9 */
|
||||
/* F20 : EMMC_RCLK */
|
||||
/* F21 : EMMC_CLK */
|
||||
/* F22 : EMMC_RESETB */
|
||||
/* F23 : BIOS_REC */
|
||||
PAD_CFG_GPI(GPP_F23, UP_20K, DEEP),
|
||||
/* G0 : SD3_D2 */
|
||||
/* G1 : SD3_D0_SD4_RCLK_P */
|
||||
/* G2 : SD3_D1_SD4_RCLK_N */
|
||||
/* G3 : SD3_D2 */
|
||||
/* G4 : SD3_D3 */
|
||||
/* G5 : SD3_CDB */
|
||||
PAD_CFG_NF(GPP_G5, UP_20K, DEEP, NF1),
|
||||
/* G6 : SD3_CLK */
|
||||
/* G7 : SD3_WP */
|
||||
PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
|
||||
|
||||
/* H0 : SSP2_SCLK */
|
||||
/* H1 : SSP2_SFRM */
|
||||
/* H2 : SSP2_TXD */
|
||||
/* H3 : SSP2_RXD */
|
||||
/* H4 : I2C2_SDA */
|
||||
/* H5 : I2C2_SCL */
|
||||
/* H6 : I2C3_SDA */
|
||||
PAD_CFG_NF(GPP_H6, UP_2K, DEEP, NF1),
|
||||
/* H7 : I2C3_SCL */
|
||||
PAD_CFG_NF(GPP_H7, UP_2K, DEEP, NF1),
|
||||
/* H8 : I2C4_SDA */
|
||||
/* H9 : I2C4_SCL */
|
||||
/* H10 : I2C5_SDA_ISH_I2C2_SDA */
|
||||
PAD_CFG_GPO(GPP_H10, 1, PLTRST),
|
||||
/* H11 : I2C5_SCL_ISH_I2C2_SCL */
|
||||
PAD_CFG_GPO(GPP_H11, 1, PLTRST),
|
||||
/* H12 : M2_SKT2_CFG_0_DFLEXIO_0 */
|
||||
PAD_CFG_GPO(GPP_H12, 1, PLTRST),
|
||||
/* H13 : M2_SKT2_CFG_1_DFLEXIO_1 */
|
||||
PAD_CFG_GPO(GPP_H13, 1, PLTRST),
|
||||
/* H14 : M2_SKT2_CFG_2 */
|
||||
PAD_CFG_GPO(GPP_H14, 0, PLTRST),
|
||||
/* H15 : M2_SKT2_CFG_3 */
|
||||
PAD_CFG_GPO(GPP_H15, 1, PLTRST),
|
||||
/* H16 : CAM5_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_H16, 1, PLTRST),
|
||||
/* H17 : CAM5_FLASH_STROBE */
|
||||
PAD_CFG_GPO(GPP_H17, 1, PLTRST),
|
||||
/* H18 : BOOTMPC */
|
||||
/* H19 : TIMESYNC_0 */
|
||||
PAD_CFG_GPO(GPP_H19, 1, PLTRST),
|
||||
/* H20 : IMGCLKOUT_1 */
|
||||
/* H21 : GPPC_H_21 */
|
||||
/* H22 : GPPC_H_22 */
|
||||
PAD_CFG_GPO(GPP_H22, 1, PLTRST),
|
||||
/* H23 : GPPC_H_23 */
|
||||
|
||||
/* GPD */
|
||||
/* GPD_0 : BATLOWB */
|
||||
/* GPD_1 : ACPRESENT */
|
||||
/* GPD_2 : LAN_WAKEB */
|
||||
/* GPD_3 : PWRBTNB */
|
||||
/* GPD_4 : SLP_S3B */
|
||||
/* GPD_5 : SLP_S4B */
|
||||
/* GPD_6 : SLP_AB */
|
||||
/* GPD_7 : GPD_7 */
|
||||
/* GPD-8 : SUSCLK */
|
||||
/* GPD-9 : SLP_WLANB */
|
||||
/* GPD-10 : SLP_5B */
|
||||
/* GPD_11 : LANPHYPC */
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
|
||||
|
||||
};
|
||||
|
||||
const struct pad_config *__weak variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *__weak
|
||||
variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
|
||||
const struct cros_gpio * __weak variant_cros_gpios(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(cros_gpios);
|
||||
return cros_gpios;
|
||||
}
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __BASEBOARD_GPIO_H__
|
||||
#define __BASEBOARD_GPIO_H__
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#endif /* __BASEBOARD_GPIO_H__ */
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __BASEBOARD_VARIANTS_H__
|
||||
#define __BASEBOARD_VARIANTS_H__
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include <stdint.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
/* The next set of functions return the gpio table and fill in the number of
|
||||
* entries for each table. */
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num);
|
||||
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num);
|
||||
|
||||
/* Seed the NHLT tables with the board specific information. */
|
||||
struct nhlt;
|
||||
void variant_nhlt_init(struct nhlt *nhlt);
|
||||
|
||||
#endif /*__BASEBOARD_VARIANTS_H__ */
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <compiler.h>
|
||||
#include <console/console.h>
|
||||
#include <nhlt.h>
|
||||
#include <soc/nhlt.h>
|
||||
|
||||
void __weak variant_nhlt_init(struct nhlt *nhlt)
|
||||
{
|
||||
/* 1-dmic configuration */
|
||||
if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&
|
||||
!nhlt_soc_add_dmic_array(nhlt, 1))
|
||||
printk(BIOS_ERR, "Added 1CH DMIC array.\n");
|
||||
/* 2-dmic configuration */
|
||||
if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) &&
|
||||
!nhlt_soc_add_dmic_array(nhlt, 2))
|
||||
printk(BIOS_ERR, "Added 2CH DMIC array.\n");
|
||||
/* 4-dmic configuration */
|
||||
if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) &&
|
||||
!nhlt_soc_add_dmic_array(nhlt, 4))
|
||||
printk(BIOS_ERR, "Added 4CH DMIC array.\n");
|
||||
|
||||
if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT)) {
|
||||
/* Dialog for Headset codec.
|
||||
* Headset codec is bi-directional but uses the same
|
||||
* configuration settings for render and capture endpoints.
|
||||
*/
|
||||
if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2))
|
||||
printk(BIOS_ERR, "Added Dialog_7219 codec.\n");
|
||||
|
||||
/* MAXIM Smart Amps for left and right speakers. */
|
||||
if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP1))
|
||||
printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98373_NHLT) &&
|
||||
!nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP1))
|
||||
printk(BIOS_ERR, "Added Maxim_98373 codec.\n");
|
||||
}
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
chip soc/intel/cannonlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
# FSP configuration
|
||||
register "SaGv" = "3"
|
||||
register "SmbusEnable" = "1"
|
||||
register "ScsEmmcEnabled" = "1"
|
||||
register "ScsEmmcHs400Enabled" = "1"
|
||||
register "ScsSdCardEnabled" = "1"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[6]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
|
||||
register "PchHdaDspEnable" = "1"
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
register "PchHdaAudioLinkSsp0" = "1"
|
||||
register "PchHdaAudioLinkSsp1" = "1"
|
||||
|
||||
register "PcieRpEnable[0]" = "1"
|
||||
register "PcieRpEnable[1]" = "1"
|
||||
register "PcieRpEnable[2]" = "1"
|
||||
register "PcieRpEnable[3]" = "1"
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpEnable[5]" = "1"
|
||||
register "PcieRpEnable[6]" = "1"
|
||||
register "PcieRpEnable[7]" = "1"
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpEnable[9]" = "1"
|
||||
register "PcieRpEnable[10]" = "1"
|
||||
register "PcieRpEnable[11]" = "1"
|
||||
register "PcieRpEnable[12]" = "1"
|
||||
register "PcieRpEnable[13]" = "1"
|
||||
|
||||
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[1]" = "8"
|
||||
register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
|
||||
register "PcieClkSrcUsage[3]" = "14"
|
||||
register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
|
||||
register "PcieClkSrcUsage[5]" = "1"
|
||||
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
register "PcieClkSrcClkReq[5]" = "5"
|
||||
|
||||
# Enable "Intel Speed Shift Technology"
|
||||
register "speed_shift_enable" = "1"
|
||||
|
||||
# GPIO for SD card detect
|
||||
register "sdcard_cd_gpio" = "GPP_G5"
|
||||
|
||||
# Enable S0ix
|
||||
register "s0ix_enable" = "1"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 04.0 on end # SA Thermal device
|
||||
device pci 12.0 on end # Thermal Subsystem
|
||||
device pci 12.5 off end # UFS SCS
|
||||
device pci 12.6 off end # GSPI #2
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.3 on end # CNVi wifi
|
||||
device pci 14.5 on end # SDCard
|
||||
device pci 15.0 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ALPS0001""
|
||||
register "generic.desc" = ""Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
|
||||
register "hid_desc_reg_offset" = "0x1"
|
||||
device i2c 2C on end
|
||||
end
|
||||
end # I2C 0
|
||||
device pci 15.1 on end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 on end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 16.5 off end # Management Engine Interface 4
|
||||
device pci 17.0 off end # SATA
|
||||
device pci 19.0 on end # I2C #4
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 on end # UART #2
|
||||
device pci 1a.0 on end # eMMC
|
||||
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
|
||||
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on end # PCI Express Port 9
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1d.4 off end # PCI Express Port 13
|
||||
device pci 1d.5 off end # PCI Express Port 14
|
||||
device pci 1d.6 off end # PCI Express Port 15
|
||||
device pci 1d.7 off end # PCI Express Port 16
|
||||
device pci 1e.0 on end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 off end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __MAINBOARD_GPIO_H__
|
||||
#define __MAINBOARD_GPIO_H__
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#endif /* __MAINBOARD_GPIO_H__ */
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
chip soc/intel/cannonlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
# FSP configuration
|
||||
register "SaGv" = "3"
|
||||
register "SmbusEnable" = "1"
|
||||
register "ScsEmmcEnabled" = "1"
|
||||
register "ScsEmmcHs400Enabled" = "1"
|
||||
register "ScsSdCardEnabled" = "1"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
|
||||
register "PchHdaDspEnable" = "1"
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
|
||||
register "PcieRpEnable[0]" = "1"
|
||||
register "PcieRpEnable[1]" = "1"
|
||||
register "PcieRpEnable[2]" = "1"
|
||||
register "PcieRpEnable[3]" = "1"
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpEnable[5]" = "1"
|
||||
register "PcieRpEnable[6]" = "1"
|
||||
register "PcieRpEnable[7]" = "1"
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpEnable[9]" = "1"
|
||||
register "PcieRpEnable[10]" = "1"
|
||||
register "PcieRpEnable[11]" = "1"
|
||||
register "PcieRpEnable[12]" = "1"
|
||||
register "PcieRpEnable[13]" = "1"
|
||||
register "PcieRpEnable[14]" = "1"
|
||||
register "PcieRpEnable[15]" = "1"
|
||||
|
||||
register "PcieClkSrcUsage[0]" = "1"
|
||||
register "PcieClkSrcUsage[1]" = "8"
|
||||
register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
|
||||
register "PcieClkSrcUsage[3]" = "13"
|
||||
register "PcieClkSrcUsage[4]" = "4"
|
||||
register "PcieClkSrcUsage[5]" = "14"
|
||||
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
register "PcieClkSrcClkReq[5]" = "5"
|
||||
|
||||
# Enable "Intel Speed Shift Technology"
|
||||
register "speed_shift_enable" = "1"
|
||||
|
||||
# GPIO for SD card detect
|
||||
register "sdcard_cd_gpio" = "GPP_G5"
|
||||
|
||||
# Enable S0ix
|
||||
register "s0ix_enable" = "1"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
|
||||
#| I2C3 | Audio |
|
||||
#+-------------------+---------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
.i2c[3] = {
|
||||
.speed = I2C_SPEED_STANDARD,
|
||||
.rise_time_ns = 104,
|
||||
.fall_time_ns = 52,
|
||||
},
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 04.0 on end # SA Thermal device
|
||||
device pci 12.0 on end # Thermal Subsystem
|
||||
device pci 12.5 off end # UFS SCS
|
||||
device pci 12.6 off end # GSPI #2
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.3 on end # CNVi wifi
|
||||
device pci 14.5 on end # SDCard
|
||||
device pci 15.0 on end # I2C #0
|
||||
device pci 15.1 on end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 on
|
||||
chip drivers/i2c/max98373
|
||||
register "interleave_mode" = "1"
|
||||
register "vmon_slot_no" = "4"
|
||||
register "imon_slot_no" = "5"
|
||||
register "uid" = "0"
|
||||
register "desc" = ""Right Speaker Amp""
|
||||
register "name" = ""MAXR""
|
||||
device i2c 32 on end
|
||||
end
|
||||
end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 16.5 off end # Management Engine Interface 4
|
||||
device pci 17.0 off end # SATA
|
||||
device pci 19.0 on end # I2C #4
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 on end # UART #2
|
||||
device pci 1a.0 on end # eMMC
|
||||
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
|
||||
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on end # PCI Express Port 9
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1d.4 off end # PCI Express Port 13
|
||||
device pci 1d.5 off end # PCI Express Port 14
|
||||
device pci 1d.6 off end # PCI Express Port 15
|
||||
device pci 1d.7 off end # PCI Express Port 16
|
||||
device pci 1e.0 on end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __MAINBOARD_GPIO_H__
|
||||
#define __MAINBOARD_GPIO_H__
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#endif /* __MAINBOARD_GPIO_H__ */
|
||||
Loading…
Reference in New Issue