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urara: add config of SPI bus and correct selection of winbond flash 

Urara uses SPFI interface 1 and Winbond SPI NOR flash.

BRANCH=none
BUG=chrome-os-partner:31438

TEST=with the fix of the Winbond driver (next patch) the bootblock
     successfully probes the Windbond device on the FPGA board.
     Console log below:

   coreboot-4.0 bootblock Tue Nov 11 07:05:48 PST 2014 starting...
   SF: Detected W25Q16 with page size 1000, total 200000

Change-Id: Ia848eac5b4a94bf95297c928b5447463c90d89eb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 38386715c52526edbe9ad356945849e21799fd94
Original-Change-Id: Ic27b60adc26bf244e7a15b5257e94df4b9d88249
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229030
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9809
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ionela Voinescu 2014-11-11 13:39:18 +00:00 committed by Patrick Georgi
parent 8549797b30
commit dfd441d1a5
1 changed files with 5 additions and 1 deletions
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6
src/mainboard/google/urara/Kconfig
View File

@ -27,7 +27,7 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ID_SUPPORT select BOARD_ID_SUPPORT
select BOOTBLOCK_CONSOLE select BOOTBLOCK_CONSOLE
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select CONFIG_SPI_FLASH_WINBOND select SPI_FLASH_WINBOND
select CPU_IMGTEC_PISTACHIO select CPU_IMGTEC_PISTACHIO
select COMMON_CBFS_SPI_WRAPPER select COMMON_CBFS_SPI_WRAPPER
select MAINBOARD_HAS_BOOTBLOCK_INIT select MAINBOARD_HAS_BOOTBLOCK_INIT
@ -58,4 +58,8 @@ config CONSOLE_SERIAL_UART_ADDRESS
depends on DRIVERS_UART depends on DRIVERS_UART
default 0xB8101500 default 0xB8101500
config BOOT_MEDIA_SPI_BUS
int
default 1
endif endif