samus: Declare TPM in devicetree.cb and include ACPI device

This adds the TPM device to the devicetree and configures an
active high edge triggered interrupt at IRQ10 and adds the ACPI
Device for the TPM into the DSDT.

It also cleans up the EC PNP ID to use the EISAID for an EC since
there are now two PNP devices declared, and removes the unused
ENABLE_TPM define at the top of the DSDT.

BUG=chrome-os-partner:33385
BRANCH=samus
TEST=build and boot on samus, ensure TPM is functional at IRQ10
CQ-DEPEND=CL:226661

Change-Id: I4b9b016014d136fbf9a37003003632821ae93a53
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0420e27b05d0f1568efa9beb849e0e8ff5995c86
Original-Change-Id: I2660cb30ac535da0b255603a619b9c09681ca947
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226663
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Duncan Laurie 2014-10-30 15:23:52 -07:00 committed by Patrick Georgi
parent b22765e0c7
commit dfdc2bac85
3 changed files with 16 additions and 7 deletions

View File

@ -57,6 +57,14 @@ Scope (\_SB)
} }
} }
/*
* LPC Trusted Platform Module
*/
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/tpm/acpi/tpm.asl>
}
/* /*
* WLAN connected to Root Port 3, becomes Root Port 1 after coalesce * WLAN connected to Root Port 3, becomes Root Port 1 after coalesce
*/ */

View File

@ -94,13 +94,16 @@ chip soc/intel/broadwell
device pci 1d.0 off end # USB2 EHCI device pci 1d.0 off end # USB2 EHCI
device pci 1e.0 off end # PCI bridge device pci 1e.0 off end # PCI bridge
device pci 1f.0 on device pci 1f.0 on
chip ec/google/chromeec chip drivers/pc80/tpm
# We only have one init function that # Rising edge interrupt
# we need to call to initialize the register "irq_polarity" = "2"
# keyboard part of the EC. device pnp 0c31.0 on
device pnp ff.1 on # dummy address irq 0x70 = 10
end end
end end
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end # LPC bridge end # LPC bridge
device pci 1f.2 on end # SATA Controller device pci 1f.2 on end # SATA Controller
device pci 1f.3 off end # SMBus device pci 1f.3 off end # SMBus

View File

@ -18,8 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#define ENABLE_TPM
DefinitionBlock( DefinitionBlock(
"dsdt.aml", "dsdt.aml",
"DSDT", "DSDT",