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fix model 106cx 

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-12-12 00:37:41 +00:00 committed by Stefan Reinauer
parent 4041925039
commit dfeb04d463
1 changed files with 8 additions and 6 deletions
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14
src/cpu/intel/model_106cx/model_106cx_init.c
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@ -97,14 +97,16 @@ static void configure_c_states(void)
// TODO Do we want Deep C4 and Dynamic L2 shrinking?
wrmsr(PMG_CST_CONFIG_CONTROL, msr);
// set P_BLK address
msr = rdmsr(PMG_IO_BASE_ADDR);
msr.lo = (PMB0 + 4) | (PMB1 << 16);
/* Set Processor MWAIT IO BASE (P_BLK) */
msr.hi = 0;
// TODO Do we want PM1_BASE? Needs SMM?
//msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
msr.lo = ((PMB0_BASE + 4) & 0xffff);
wrmsr(PMG_IO_BASE_ADDR, msr);
// set C_LVL controls
msr = rdmsr(PMG_IO_CAPTURE_ADDR);
msr.lo = (PMB0 + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
/* set C_LVL controls */
msr.hi = 0;
msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
wrmsr(PMG_IO_CAPTURE_ADDR, msr);
}