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We currently read the CPU HT speed from HT chain 0's register. 

Fix that to read the register from the chain where the SB chip is on.

Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Liu Tao 2010-10-17 21:34:45 +00:00 committed by Uwe Hermann
parent c6a106286b
commit dfecd2740b
1 changed files with 8 additions and 2 deletions
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10
src/southbridge/amd/rs780/rs780_gfx.c
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@ -304,7 +304,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
volatile u32 * pointer; volatile u32 * pointer;
int i; int i;
u16 command; u16 command;
u32 value; u32 value, sblink;
u16 deviceid, vendorid; u16 deviceid, vendorid;
device_t nb_dev = dev_find_slot(0, 0); device_t nb_dev = dev_find_slot(0, 0);
device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
@ -453,9 +453,15 @@ static void internal_gfx_pci_dev_init(struct device *dev)
vgainfo.usMinNBVoltage = 0; vgainfo.usMinNBVoltage = 0;
vgainfo.usBootUpNBVoltage = 0x1a; vgainfo.usBootUpNBVoltage = 0x1a;
/* Get SBLink value (HyperTransport I/O Hub Link ID). */
value = pci_read_config32(k8_f0, 0x64);
sblink = (value >> 8) & 0x3;
printk(BIOS_DEBUG, "SBLINK = %d.\n", sblink);
/* HT speed */
value = pci_read_config32(nb_dev, 0xd0); value = pci_read_config32(nb_dev, 0xd0);
printk(BIOS_DEBUG, "NB HT speed = %x.\n", value); printk(BIOS_DEBUG, "NB HT speed = %x.\n", value);
value = pci_read_config32(k8_f0, 0x88); value = pci_read_config32(k8_f0, 0x88 + (sblink * 0x20));
printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value); printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value);
vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */ vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */