diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 353bdbe891..2852b6a652 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -2,6 +2,8 @@
 
 ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
 
+subdirs-y += ../../../cpu/x86/mtrr
+
 # Beware that all-y also adds the compilation unit to verstage on PSP
 all-y += config.c
 
diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c
index 9fb99bdca2..d1479da6f4 100644
--- a/src/soc/amd/cezanne/bootblock.c
+++ b/src/soc/amd/cezanne/bootblock.c
@@ -3,12 +3,91 @@
 #include <amdblocks/amd_pci_mmconf.h>
 #include <bootblock_common.h>
 #include <console/console.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/x86/tsc.h>
+#include <soc/iomap.h>
 #include <soc/southbridge.h>
 #include <stdint.h>
 
+/*
+ * PSP performs the memory training and setting up DRAM map prior to x86 cores being released.
+ * Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, route lower memory addresses
+ * covered by fixed MTRRs to DRAM except for 0xa0000-0xc0000.
+ */
+static void set_caching(void)
+{
+	msr_t top_mem;
+	msr_t sys_cfg;
+	msr_t mtrr_def_type;
+	msr_t fixed_mtrr_ram;
+	msr_t fixed_mtrr_mmio;
+	struct var_mtrr_context mtrr_ctx;
+
+	var_mtrr_context_init(&mtrr_ctx, NULL);
+	top_mem = rdmsr(TOP_MEM);
+	/* Enable RdDram and WrDram attributes in fixed MTRRs. */
+	sys_cfg = rdmsr(SYSCFG_MSR);
+	sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+
+	/* Fixed MTRR constants. */
+	fixed_mtrr_ram.lo = fixed_mtrr_ram.hi =
+		((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) <<  0) |
+		((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) <<  8) |
+		((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) |
+		((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24);
+	fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi =
+		((MTRR_TYPE_UNCACHEABLE) <<  0) |
+		((MTRR_TYPE_UNCACHEABLE) <<  8) |
+		((MTRR_TYPE_UNCACHEABLE) << 16) |
+		((MTRR_TYPE_UNCACHEABLE) << 24);
+
+	/* Prep default MTRR type. */
+	mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR);
+	mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK;
+	mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE;
+	mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN;
+
+	disable_cache();
+
+	wrmsr(SYSCFG_MSR, sys_cfg);
+
+	clear_all_var_mtrr();
+
+	var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK);
+	/* TODO: check if we should always mark 16 MByte below 4 GByte as WRPROT */
+	var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+
+	/* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */
+	wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio);
+	wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram);
+
+	wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type);
+
+	/* Enable Fixed and Variable MTRRs. */
+	sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn;
+	sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB;
+	/* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once
+	   MP init happens in coreboot proper it can be knocked down. */
+	wrmsr(SYSCFG_MSR, sys_cfg);
+
+	enable_cache();
+}
+
 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
+	set_caching();
 	enable_pci_mmconf();
 
 	/*
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
index 4d47f7ed57..b377ee31fb 100644
--- a/src/soc/amd/cezanne/include/soc/iomap.h
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -3,6 +3,9 @@
 #ifndef AMD_CEZANNE_IOMAP_H
 #define AMD_CEZANNE_IOMAP_H
 
+/* MMIO Ranges */
+#define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)
+
 /* I/O Ranges */
 #define NCP_ERR				0x00f0
 #define SMB_BASE_ADDR			0x0b00