From e0060a80f0b662f9e4693785baaac16acb96632b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 5 Mar 2020 08:06:27 -0800 Subject: [PATCH] ec/google/chromeec: Fix dev ops for chromeec CB:38541 ("ec/google/chromeec: Add SSDT generator for ChromeOS EC") added a new device_operations structure for chromeec for handling ACPI SSDT generation. However, this resulted in the original device_operations which handled lpc read resources to be skipped. This change fixes the above regression by combining the device operations for reading resources and ACPI SSDT generation into a single structure and retains the old logic for enabling of pnp devices. Signed-off-by: Furquan Shaikh Change-Id: I3a242f4b15603f957e0e81d121e5766fccf3c28d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39321 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Matt DeVillier Reviewed-by: Nico Huber --- src/ec/google/chromeec/Makefile.inc | 2 +- src/ec/google/chromeec/ec.c | 25 ------------------- src/ec/google/chromeec/ec.h | 5 ---- .../google/chromeec/{ec_chip.c => ec_acpi.c} | 0 src/ec/google/chromeec/ec_lpc.c | 13 ++++++++-- 5 files changed, 12 insertions(+), 33 deletions(-) rename src/ec/google/chromeec/{ec_chip.c => ec_acpi.c} (100%) diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 2833c87d33..590b131355 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -28,7 +28,7 @@ verstage-y += ec.c crosec_proto.c vstore.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_chip.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_acpi.c ramstage-$(CONFIG_VBOOT) += vboot_storage.c smm-$(CONFIG_VBOOT) += vboot_storage.c diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 81e68d0f96..3faa29778b 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1525,28 +1525,3 @@ int google_chromeec_wait_for_displayport(long timeout) return 1; } - -#if CONFIG(HAVE_ACPI_TABLES) && !DEVTREE_EARLY -static struct device_operations ec_chromeec_ops = { - .acpi_name = google_chromeec_acpi_name, - .acpi_fill_ssdt_generator = google_chromeec_fill_ssdt_generator, -}; -#endif - -/* ec_lpc, ec_spi, or ec_i2c can override this */ -__weak void google_ec_enable_extra(struct device *dev) -{ -} - -static void google_chromeec_enable(struct device *dev) -{ -#if CONFIG(HAVE_ACPI_TABLES) && !DEVTREE_EARLY - dev->ops = &ec_chromeec_ops; -#endif - google_ec_enable_extra(dev); -} - -struct chip_operations ec_google_chromeec_ops = { - CHIP_NAME("Google Chrome EC") - .enable_dev = google_chromeec_enable -}; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f13b5105c2..699d7c2793 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -350,9 +350,4 @@ const char *google_chromeec_acpi_name(const struct device *dev); #endif /* HAVE_ACPI_TABLES */ -/* - * Allows bus-specific EC code to perform actions when the device is enabled. - */ -void google_ec_enable_extra(struct device *dev); - #endif /* _EC_GOOGLE_CHROMEEC_EC_H */ diff --git a/src/ec/google/chromeec/ec_chip.c b/src/ec/google/chromeec/ec_acpi.c similarity index 100% rename from src/ec/google/chromeec/ec_chip.c rename to src/ec/google/chromeec/ec_acpi.c diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 9afb1fd653..ab0e3cd38a 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -451,18 +451,27 @@ static struct device_operations ops = { .init = lpc_ec_init, .read_resources = lpc_ec_read_resources, .enable_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP + .set_resources = DEVICE_NOOP, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = google_chromeec_acpi_name, + .acpi_fill_ssdt_generator = google_chromeec_fill_ssdt_generator, +#endif }; static struct pnp_info pnp_dev_info[] = { { NULL, 0, 0, 0, } }; -void google_ec_enable_extra(struct device *dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } +struct chip_operations ec_google_chromeec_ops = { + CHIP_NAME("Google Chrome EC") + .enable_dev = enable_dev, +}; + static int google_chromeec_data_ready(u16 port) { return google_chromeec_status_check(port, EC_LPC_CMDR_DATA,