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mb/intel/mtlrvp: Enable DPTF functionality for mtlrvp board 

Enable DPTF functionality for Meteor Lake based mtlrvp board

BRANCH=None
BUG=None
TEST=Built and booted on mtlrvp board

Change-Id: I8d3e1cd43cf67c3f2081be339589a6da358b668c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Sumeet Pawnikar 2023-02-09 17:21:07 +05:30 committed by Felix Held
parent f9eeded219
commit e00705e0a0
2 changed files with 91 additions and 0 deletions
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2
src/mainboard/intel/mtlrvp/Kconfig
View File

@ -8,6 +8,8 @@ config BOARD_INTEL_MTLRVP_COMMON
select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_METEORLAKE
select DRIVERS_INTEL_DPTF
select DRIVERS_INTEL_DPTF_SUPPORTS_TPCH
config BOARD_INTEL_MTLRVP_P
select BOARD_INTEL_MTLRVP_COMMON

89
src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
View File

@ -84,8 +84,97 @@ chip soc/intel/meteorlake
[PchSerialIoIndexGSPI1] = 0,
}"
# DPTF enable
register "dptf_enable" = "1"
device domain 0 on
device ref igpu on end
device ref dtt on
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""Ambient""
register "options.tsr[1].desc" = ""DDR""
register "options.tsr[2].desc" = ""Skin""
register "options.tsr[3].desc" = ""Battery""
## Active Policy
# TODO: below values are initial reference values only
register "policies.active" = "{
[0] = {
.target = DPTF_CPU,
.thresholds = {
TEMP_PCT(95, 90),
TEMP_PCT(90, 80),
}
},
[1] = {
.target = DPTF_TEMP_SENSOR_0,
.thresholds = {
TEMP_PCT(80, 90),
TEMP_PCT(70, 80),
}
}
}"
## Passive Policy
# TODO: below values are initial reference values only
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 10000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000),
}"
## Critical Policy
# TODO: below values are initial reference values only
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN),
}"
## Power Limits Control
register "controls.power_limits" = "{
.pl1 = {
.min_power = 35000,
.max_power = 45000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,
},
.pl2 = {
.min_power = 56000,
.max_power = 56000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,
}
}"
## Charger Performance Control (Control, mA)
register "controls.charger_perf" = "{
[0] = { 255, 3000 },
[1] = { 24, 1500 },
[2] = { 16, 1000 },
[3] = { 8, 500 }
}"
## Fan Performance Control (Percent, Speed, Noise, Power)
register "controls.fan_perf" = "{
[0] = { 90, 6700, 220, 2200, },
[1] = { 80, 5800, 180, 1800, },
[2] = { 70, 5000, 145, 1450, },
[3] = { 60, 4900, 115, 1150, },
[4] = { 50, 3838, 90, 900, },
[5] = { 40, 2904, 55, 550, },
[6] = { 30, 2337, 30, 300, },
[7] = { 20, 1608, 15, 150, },
[8] = { 10, 800, 10, 100, },
[9] = { 0, 0, 0, 50, }
}"
## Fan options
register "options.fan.fine_grained_control" = "1"
register "options.fan.step_size" = "2"
device generic 0 alias dptf_policy on end
end
end
device ref heci1 on end
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp1 on end