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mb/google/arcada: Enable bayhub 720 on Arcada 

Add PCIe-eMMC bridge bayhub 720 on Arcada to the devicetree.

BUG=b:157971972
BRANCH=sarien
TEST=local build and boot from SATA/PCIe-eMMC storage successfully

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I7e925730e57806e7398684dffd0d3bd1f4f9deeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43669
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mark Hsieh 2020-07-21 18:48:42 +08:00 committed by Tim Wawrzynczak
parent 311ddbd193
commit e00db59c7c
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/sarien/variants/arcada/devicetree.cb
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@ -382,6 +382,10 @@ chip soc/intel/cannonlake
device pci 1d.2 on end # PCI Express Port 11 device pci 1d.2 on end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12 device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on device pci 1d.4 on
chip drivers/generic/bayhub
register "power_saving" = "1"
device pci 00.0 on end
end
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
end # PCI Express Port 13 (x4) end # PCI Express Port 13 (x4)
device pci 1e.0 off end # UART #0 device pci 1e.0 off end # UART #0