mb/google/brya/variant/taeko: Update devicetree settings
Based on schematic and gpio table of taeko, generate overridetree.cb settings for taeko. BUG=b:195494281 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I96aaf48284a226edc39115f870bf0f3dd83ab8b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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chip soc/intel/alderlake
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register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # DB USB2_C1
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register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN
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register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN
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device domain 0 on
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end
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
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#| GSPI1 | Fingerprint MCU |
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#| I2C0 | Audio |
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#| I2C1 | Touchscreen |
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#| I2C2 | HPS |
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#| I2C3 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
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register "common_soc_config" = "{
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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# I2C Port Config
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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device domain 0 on
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device ref tbt_pcie_rp0 off end
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device ref tbt_pcie_rp1 off end
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device ref tbt_pcie_rp2 off end
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device ref i2c0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on
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end
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end
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end
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device ref i2c1 on
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chip drivers/i2c/hid
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register "generic.hid" = ""GDIX0000""
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register "generic.desc" = ""Goodix Touchscreen""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
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# Parameter T5 >= 180ms
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register "generic.reset_delay_ms" = "180"
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# Parameter T2 >= 1ms
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register "generic.reset_off_delay_ms" = "3"
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register "generic.enable_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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# Parameter T1 >= 20ms
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register "generic.enable_delay_ms" = "20"
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register "generic.stop_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)"
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# Parameter T4 >= 1ms
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register "generic.stop_off_delay_ms" = "1"
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register "generic.has_power_resource" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 5d on end
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end
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
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register "probed" = "1"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
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register "reset_delay_ms" = "20"
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register "enable_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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register "enable_delay_ms" = "1"
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register "has_power_resource" = "1"
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device i2c 10 on end
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end
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end
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device ref i2c5 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
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register "wake" = "GPE0_DW2_15"
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register "probed" = "1"
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device i2c 15 on end
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end
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chip drivers/i2c/hid
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register "generic.hid" = ""PNP0C50""
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register "generic.desc" = ""Synaptics Touchpad""
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register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
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register "generic.wake" = "GPE0_DW2_15"
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register "generic.probed" = "1"
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register "hid_desc_reg_offset" = "0x20"
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device i2c 2c on end
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end
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end
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device ref hda on
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chip drivers/generic/max98357a
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register "hid" = ""MX98357A""
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register "sdmode_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
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register "sdmode_delay" = "5"
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device generic 0 on end
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end
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chip drivers/intel/soundwire
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device generic 0 on
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chip drivers/soundwire/alc5682
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# SoundWire Link 0 ID 1
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register "desc" = ""Headset Codec""
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device generic 0.1 on end
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end
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chip drivers/soundwire/max98373
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# SoundWire Link 2 ID 3
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register "desc" = ""Left Speaker Amp""
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device generic 2.3 on end
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end
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chip drivers/soundwire/max98373
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# SoundWire Link 2 ID 7
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register "desc" = ""Right Speaker Amp""
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device generic 2.7 on end
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end
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end
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end
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end
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device ref pcie_rp5 on
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
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register "srcclk_pin" = "2"
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device generic 0 on end
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end
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end
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device ref pcie_rp6 off end
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device ref pcie_rp8 on
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
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register "srcclk_pin" = "3"
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device generic 0 on end
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end
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end
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device ref pcie_rp9 on
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
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register "srcclk_pin" = "1"
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device generic 0 on end
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end
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end
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device ref gspi1 on
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chip drivers/spi/acpi
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register "name" = ""CRFP""
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "uid" = "1"
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register "compat_string" = ""google,cros-ec-spi""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
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register "wake" = "GPE0_DW2_15"
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device spi 0 on end
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end # FPMCU
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end
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device ref pch_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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register "usb2_port_number" = "1"
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register "usb3_port_number" = "1"
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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register "usb2_port_number" = "3"
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register "usb3_port_number" = "3"
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device generic 2 alias conn1 on end
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end
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(3, 1)"
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device ref tcss_usb3_port3 on end
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end
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end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(3, 1)"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Camera""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port6 on
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end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port (MLB)""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(4, 1)"
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device ref usb2_port9 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
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device ref usb2_port10 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(4, 1)"
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device ref usb3_port1 on end
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end
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end
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end
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end
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end
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end
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