mb/google/skyrim: Enable fingerprint sensor in Skyrim

Add fingerprint device and select UART_ACPI driver.
Disable FPMCU until the proper boot segment initializes it.

BUG=b:228271993
BRANCH=NONE
TEST=Can add fingerprints and unlock the device using them.

Signed-off-by: Moises Garcia <moisesgarcia@google.com>
Change-Id: I71e1c7d654395284cdec43bb6e5f581e546da36a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65299
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Moises Garcia 2022-06-21 15:05:08 -07:00 committed by Raul Rangel
parent eb3e0985b8
commit e046062ba6
3 changed files with 22 additions and 1 deletions

View File

@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
select DRIVERS_I2C_HID
select DRIVERS_I2C_NAU8825
select DRIVERS_USB_HUB
select DRIVERS_UART_ACPI
select DRIVERS_WIFI_GENERIC
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI

View File

@ -16,7 +16,7 @@ static const struct soc_amd_gpio base_gpio_table[] = {
/* SOC_PEN_DETECT_ODL */
PAD_WAKE(GPIO_3, PULL_NONE, EDGE_LOW, S0i3),
/* EN_PWR_FP */
PAD_GPO(GPIO_4, HIGH),
PAD_GPO(GPIO_4, LOW),
/* EN_PP3300_TCHPAD */
PAD_GPO(GPIO_5, HIGH),
/* SSD_AUX_RESET_L */

View File

@ -221,4 +221,24 @@ chip soc/amd/sabrina
probe AUDIO_DB AUDIO_DB_C_NAU88L25YGB_A_MAX98360AENL
end
end
device ref uart_1 on
chip drivers/uart/acpi
register "name" = ""CRFP""
register "desc" = ""Fingerprint Reader""
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cros-ec-uart""
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)"
register "wake" = "GEVENT_15"
register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
register "has_power_resource" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_4)"
register "enable_delay_ms" = "3"
device generic 0 alias fpmcu on
probe FP FP_PRESENT
end
end
end # UART1
end # chip soc/amd/sabrina