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mb/amd/chausie/devicetree: update I2C RX levels to match board design 

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie5d5f5441132e5b0d8991d07d4dde994fc17ab64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2022-02-02 22:54:05 +01:00
parent 556d1cc17f
commit e04be37806
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/amd/chausie/devicetree.cb
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@ -14,10 +14,10 @@ chip soc/amd/sabrina
}"
# I2C Pad Control RX Select Configuration
register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V"
register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V"
register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V"
register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V"
register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V"
register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V"
register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V"
register "s0ix_enable" = "true"