asus/a8n-e: Implement basic ACPI.
Change-Id: I3c8fa1fbec2175787666697f2239abb70020019e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4819 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Vladimir Serbinenko
parent
8540a8b80f
commit
e0553b436b
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@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select CK804_USE_NIC
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select CK804_USE_ACI
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select QRANK_DIMM_SUPPORT
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select HAVE_ACPI_TABLES
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config MAINBOARD_DIR
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string
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@ -0,0 +1,201 @@
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/*
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* ACPI support
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* written by Stefan Reinauer <stepan@openbios.org>
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* (C) 2005 Stefan Reinauer
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*
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*
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* Copyright 2005 AMD
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* 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
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*/
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#include <console/console.h>
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#include <string.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/amd/amdk8_sysconf.h>
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#include "../../../northbridge/amd/amdk8/acpi.h"
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//#include <cpu/amd/model_fxx_powernow.h>
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extern const unsigned char AmlCode[];
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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device_t dev;
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unsigned long mcfg_base;
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dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0));
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if (!dev)
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return current;
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mcfg_base = pci_read_config16(dev, 0x90);
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if ((mcfg_base & 0x1000) == 0)
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return current;
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mcfg_base = (mcfg_base & 0xf) << 28;
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printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base);
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
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current, mcfg_base, 0x0, 0x0, 0xff);
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return current;
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}
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/* APIC */
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unsigned long acpi_fill_madt(unsigned long current)
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{
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device_t dev;
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struct resource *res;
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/* create all subtables for processors */
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current = acpi_create_madt_lapics(current);
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/* Write NVIDIA CK804 IOAPIC. */
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dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
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ASSERT(dev != NULL);
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res = find_resource(dev, PCI_BASE_ADDRESS_1);
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ASSERT(res != NULL);
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
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CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0);
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/* Initialize interrupt mapping if mptable.c didn't. */
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#if (!CONFIG_GENERATE_MP_TABLE)
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#error untested config
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pci_write_config32(dev, 0x7c, 0x0120d218);
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pci_write_config32(dev, 0x80, 0x12008a00);
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pci_write_config32(dev, 0x84, 0x0000007d);
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#endif
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/* IRQ of timer */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 0, 2, 0);
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/* IRQ9 */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
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/* create all subtables for processors */
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/* acpi_create_madt_lapic_nmis returns current, not size. */
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current = acpi_create_madt_lapic_nmis(current,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
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return current;
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}
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unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) {
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k8acpi_write_vars();
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//amd_model_fxx_generate_powernow(0, 0, 0);
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return (unsigned long) (acpigen_get_current());
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}
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unsigned long write_acpi_tables(unsigned long start)
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{
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unsigned long current;
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acpi_rsdp_t *rsdp;
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acpi_srat_t *srat;
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acpi_rsdt_t *rsdt;
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acpi_hpet_t *hpet;
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acpi_madt_t *madt;
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acpi_mcfg_t *mcfg;
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acpi_fadt_t *fadt;
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acpi_facs_t *facs;
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acpi_slit_t *slit;
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acpi_header_t *ssdt;
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acpi_header_t *dsdt;
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/* Align ACPI tables to 16 byte. */
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start = ALIGN(start, 16);
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current = start;
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printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
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/* We need at least an RSDP and an RSDT Table */
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rsdp = (acpi_rsdp_t *) current;
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current += sizeof(acpi_rsdp_t);
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current = ALIGN(current, 16);
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rsdt = (acpi_rsdt_t *) current;
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current += sizeof(acpi_rsdt_t);
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/* Clear all table memory. */
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memset((void *) start, 0, current - start);
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acpi_write_rsdp(rsdp, rsdt, NULL);
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acpi_write_rsdt(rsdt);
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current = ALIGN(current, 64);
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facs = (acpi_facs_t *) current;
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printk(BIOS_DEBUG, "ACPI: * FACS %p\n", facs);
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current += sizeof(acpi_facs_t);
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acpi_create_facs(facs);
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/* DSDT */
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current = ALIGN(current, 16);
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dsdt = (acpi_header_t *) current;
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printk(BIOS_DEBUG, "ACPI: * DSDT %p\n", dsdt);
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memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
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current += dsdt->length;
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memcpy(dsdt, &AmlCode, dsdt->length);
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printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
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current = ALIGN(current, 16);
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fadt = (acpi_fadt_t *) current;
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printk(BIOS_DEBUG, "ACPI: * FACP (FADT) @ %p\n", fadt);
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current += sizeof(acpi_fadt_t);
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/* Add FADT now that we have facs and dsdt. */
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acpi_create_fadt(fadt, facs, dsdt);
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acpi_add_table(rsdp, fadt);
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current = ALIGN(current, 16);
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mcfg = (acpi_mcfg_t *) current;
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printk(BIOS_DEBUG, "ACPI: * MCFG @ %p\n", mcfg);
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acpi_create_mcfg(mcfg);
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current += mcfg->header.length;
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acpi_add_table(rsdp, mcfg);
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current = ALIGN(current, 16);
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hpet = (acpi_hpet_t *) current;
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printk(BIOS_DEBUG, "ACPI: * HPET @ %p\n", hpet);
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acpi_create_hpet(hpet);
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acpi_add_table(rsdp, hpet);
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current += hpet->header.length;
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current = ALIGN(current, 16);
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madt = (acpi_madt_t *) current;
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printk(BIOS_DEBUG, "ACPI: * APIC/MADT @ %p\n", madt);
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acpi_create_madt(madt);
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current += madt->header.length;
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acpi_add_table(rsdp, madt);
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current = ALIGN(current, 16);
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srat = (acpi_srat_t *) current;
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printk(BIOS_DEBUG, "ACPI: * SRAT @ %p\n", srat);
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acpi_create_srat(srat);
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current += srat->header.length;
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acpi_add_table(rsdp, srat);
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/* SLIT */
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current = ALIGN(current, 16);
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slit = (acpi_slit_t *) current;
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printk(BIOS_DEBUG, "ACPI: * SLIT @ %p\n", slit);
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acpi_create_slit(slit);
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current+=slit->header.length;
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acpi_add_table(rsdp,slit);
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/* SSDT */
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current = ALIGN(current, 16);
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ssdt = (acpi_header_t *)current;
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printk(BIOS_DEBUG, "ACPI: * SSDT @ %p\n", ssdt);
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acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
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current += ssdt->length;
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acpi_add_table(rsdp, ssdt);
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printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current);
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return current;
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}
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@ -0,0 +1,269 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
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* Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* ISA portions taken from QEMU acpi-dsdt.dsl.
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*/
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DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
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{
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#include "northbridge/amd/amdk8/util.asl"
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/* For now only define 2 power states:
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* - S0 which is fully on
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* - S5 which is soft off
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* Any others would involve declaring the wake up methods.
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*/
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Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
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Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
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Name (PICM, 0x00)
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Method (_PIC, 1, Serialized) {
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Store (Arg0, PICM)
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}
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/* Root of the bus hierarchy */
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Scope (\_SB)
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{
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/* Top PCI device (CK804) */
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Device (PCI0)
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{
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Name (_HID, EisaId ("PNP0A03"))
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Name (_ADR, 0x00)
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Name (_UID, 0x00)
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Name (_BBN, 0x00)
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External (BUSN)
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External (MMIO)
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External (PCIO)
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External (SBLK)
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External (TOM1)
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External (HCLK)
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External (SBDN)
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External (HCDN)
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF0, ResourceTemplate ()
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{
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IO (Decode16,
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0x0CF8, // Address Range Minimum
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0x0CF8, // Address Range Maximum
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0x01, // Address Alignment
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0x08, // Address Length
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)
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Address Space Granularity
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0x0000, // Address Range Minimum
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0x0CF7, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x0CF8, // Address Length
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,, , TypeStatic)
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})
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/* Methods bellow use SSDT to get actual MMIO regs
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The IO ports are from 0xd00, optionally an VGA,
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otherwise the info from MMIO is used.
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\_SB.GXXX(node, link)
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*/
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Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
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Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
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Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
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Return (Local3)
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}
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#include "southbridge/nvidia/ck804/acpi/ck804.asl"
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/* PCI Routing Table */
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Name (_PRT, Package () {
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Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LLAS, 0x00 },//APCS
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Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LLAS, 0x00 },//APCS
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Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LUOH, 0x00 },//APCF
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Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LUEH, 0x00 },//APCL
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Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LAUD, 0x00 },//APCJ
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Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LMOD, 0x00 },//APCK
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Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LPA0, 0x00 },//APCZ
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Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 },//APSI
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Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 },//APSJ
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Package (0x04) { 0x0009FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
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Package (0x04) { 0x0009FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
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Package (0x04) { 0x0009FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
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Package (0x04) { 0x0009FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
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Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 },//APCH
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Package (0x04) { 0x000BFFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//APC2
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Package (0x04) { 0x000BFFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },//APC3
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Package (0x04) { 0x000BFFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },//APC4
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Package (0x04) { 0x000BFFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },//APC1
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Package (0x04) { 0x000CFFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//APC1
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Package (0x04) { 0x000CFFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },//APC2
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Package (0x04) { 0x000CFFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },//APC3
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Package (0x04) { 0x000CFFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },//APC4
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Package (0x04) { 0x000DFFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//APC4
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Package (0x04) { 0x000DFFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },//APC1
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Package (0x04) { 0x000DFFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },//APC2
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Package (0x04) { 0x000DFFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },//APC3
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Package (0x04) { 0x000EFFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//APC3
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Package (0x04) { 0x000EFFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },//APC4
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Package (0x04) { 0x000EFFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },//APC1
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Package (0x04) { 0x000EFFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },//APC2
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})
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Device (PCIC)
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{
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Name (_ADR, 0x00090000)
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Name (_UID, 0x00)
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Name (_PRT, Package () {
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/* AGR slot */
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
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})
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}
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/* 2:00 PCIe x1 */
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Device (PEX1)
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{
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Name (_ADR, 0x000d0000)
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Name (_UID, 0x00)
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}
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/* 3:00 PCIe x16 */
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Device (PEX0)
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{
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Name (_ADR, 0x000e0000)
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Name (_UID, 0x00)
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}
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Device (LPC) {
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Name (_HID, EisaId ("PNP0A05"))
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Name (_ADR, 0x00010000)
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OperationRegion (CF44, PCI_Config, 0x44, 0x04)
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Field (CF44, ByteAcc, NoLock, Preserve)
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{
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ETBA, 32,
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}
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/* PS/2 keyboard (seems to be important for WinXP install) */
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Device (KBD)
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{
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Name (_HID, EisaId ("PNP0303"))
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0f)
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (TMP, ResourceTemplate () {
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IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
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IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
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IRQNoFlags () {1}
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})
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Return (TMP)
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}
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}
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||||
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/* PS/2 mouse */
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Device (MOU)
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{
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Name (_HID, EisaId ("PNP0F13"))
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0f)
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (TMP, ResourceTemplate () {
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IRQNoFlags () {12}
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})
|
||||
Return (TMP)
|
||||
}
|
||||
}
|
||||
|
||||
/* Parallel port */
|
||||
Device (LP0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (TMP, ResourceTemplate () {
|
||||
FixedIO (0x0378, 0x10)
|
||||
IRQNoFlags () {7}
|
||||
})
|
||||
Return (TMP)
|
||||
}
|
||||
}
|
||||
|
||||
/* Floppy controller */
|
||||
Device (FDC0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0700"))
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate () {
|
||||
FixedIO (0x03F0, 0x08)
|
||||
IRQNoFlags () {6}
|
||||
DMA (Compatibility, NotBusMaster, Transfer8) {2}
|
||||
})
|
||||
Return (BUF0)
|
||||
}
|
||||
}
|
||||
#if 0
|
||||
Device (HPET)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0103"))
|
||||
Name (CRS, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed (ReadOnly,
|
||||
0x00000000,
|
||||
0x00001000,
|
||||
_Y02)
|
||||
})
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT)
|
||||
Store (ETBA, HPT)
|
||||
Return (CRS)
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue