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soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups 

This implementation corrects the GPE DWx mapping for GPIO groups.
The assignments is done in GPIO MISCFG register for all GPIO communities.
And configures the which GPIO communities get register as Tier1.

BUG=b:121212459
TEST: Verified the GPIO MISCFG is getting set as per updated map.

Change-Id: I451997367025a6dc9e5931bd649524e935ad6aca
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32175
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra 2019-04-03 14:42:26 +05:30 committed by Patrick Georgi
parent 4577cd2403
commit e05fe3166e
1 changed files with 13 additions and 12 deletions
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25
src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
View File

@ -22,18 +22,19 @@
* The GPIO groups are accessed through register blocks called
* communities.
*/
#define GPP_A 0
#define GPP_B 1
#define GPP_G 2
#define GROUP_SPI 3
#define GPP_D 4
#define GPP_F 5
#define GPP_H 6
#define GROUP_VGPIO 7
#define GPD 9
#define GROUP_AZA 0xA
#define GROUP_CPU 0xB
#define GPP_C 0xC
#define GPP_A 0x0
#define GPP_B 0x1
#define GPP_G 0x2
#define GROUP_SPI 0x3
#define GPP_D 0x5
#define GPP_F 0x6
#define GPP_H 0x7
#define GROUP_VGPIO0 0x8
#define GROUP_VGPIO1 0x9
#define GPD 0xA
#define GROUP_AZA 0xB
#define GROUP_CPU 0xC
#define GPP_C 0x4
#define GPP_E 0xD
#define GROUP_JTAG 0xE
#define GROUP_HVMOS 0xF