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mb/google/brya/var/vell: update overridetree for SSD setting 

Change CLKSRC#3 to CLKSRC#1 in override devicetree based on schematics

BUG=b:208756696
TEST=emerge-brya coreboot

Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37
Signed-off-by: = <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
= 2021-12-14 15:27:01 +08:00 committed by Felix Held
parent 0617d5a16f
commit e061fbf1e7
1 changed files with 2 additions and 2 deletions
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src/mainboard/google/brya/variants/vell/overridetree.cb
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@ -125,10 +125,10 @@ chip soc/intel/alderlake
end end
end end
device ref pcie4_0 on device ref pcie4_0 on
# Enable CPU PCIE RP 1 using CLK 0 # Enable CPU PCIE RP 1 using CLK 1
register "cpu_pcie_rp[CPU_RP(1)]" = "{ register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_req = 1, .clk_req = 1,
.clk_src = 3, .clk_src = 1,
}" }"
end end
device ref cnvi_wifi on device ref cnvi_wifi on