mb/google/brya/var/vell: update overridetree for SSD setting

Change CLKSRC#3 to CLKSRC#1 in override devicetree based on schematics

BUG=b:208756696
TEST=emerge-brya coreboot

Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37
Signed-off-by: = <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/brya/variants/vell/overridetree.cb

@@ -125,10 +125,10 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref pcie4_0 on
-			# Enable CPU PCIE RP 1 using CLK 0
+			# Enable CPU PCIE RP 1 using CLK 1
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_req = 1,
-				.clk_src = 3,
+				.clk_src = 1,
 			}"
 		end
 		device ref cnvi_wifi on