mainboard/google: add reef reference board
This adds the initial scaffolding for the reef reference board. One big thing missing is the GPIO configuration. Change-Id: I8e2d275df296bb397bb33dbd0c66fc87c82ff10f Signed-off-by: Aaron Durbni <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14798 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin
parent
fc2e7413b3
commit
e065bb43d7
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@ -0,0 +1,53 @@
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if BOARD_GOOGLE_REEF
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select SOC_INTEL_APOLLOLAKE
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# FIXME(adurbin): this SPI part is really 16MiB
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select BOARD_ROMSIZE_KB_8192
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_LPC
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select SYSTEM_TYPE_LAPTOP
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config BOOT_MEDIA_SPI_BUS
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int
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default 0
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config IFD_BIOS_END
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hex
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default 0x6FF000
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config IFD_BIOS_START
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hex
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default 0x1000
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config CHROMEOS
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select CHROMEOS_RAMOOPS_DYNAMIC
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select CHROMEOS_VBNV_CMOS
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select CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH
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select EC_SOFTWARE_SYNC
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select LID_SWITCH
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select VBOOT_OPROM_MATTERS
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select VIRTUAL_DEV_SWITCH
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config MAINBOARD_DIR
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string
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default google/reef
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config MAINBOARD_PART_NUMBER
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string
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default "Reef"
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config MAINBOARD_FAMILY
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string
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default "Google_Reef"
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config MAX_CPUS
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int
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default 8
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endif # BOARD_GOOGLE_REEF
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@ -0,0 +1,3 @@
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config BOARD_GOOGLE_REEF
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bool "Reef"
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@ -0,0 +1,8 @@
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bootblock-y += bootblock.c
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bootblock-y += ec.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += ec.c
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ramstage-y += mainboard.c
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@ -0,0 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/gpio_defs.h>
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Name (OIPG, Package () {
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/* No physical recovery GPIO. */
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Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:00" },
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/* Firmware write protect GPIO. */
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Package () { 0x0003, 1, GPIO_75, "INT3452:00" },
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})
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@ -0,0 +1,16 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "acpi/superio.asl"
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* mainboard configuration */
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#include "../ec.h"
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#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
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#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
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#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Blank file required by build system assumptions of this file being present.
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*/
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@ -0,0 +1,6 @@
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Vendor name: Google
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Board name: Reef Apollolake Reference Board
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Category: laptop
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <soc/lpc.h>
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#include <soc/gpio.h>
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#include "ec.h"
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#include "gpio.h"
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void bootblock_mainboard_init(void)
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{
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lpc_configure_pads();
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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mainboard_ec_init();
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}
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@ -0,0 +1,71 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <boot/coreboot_tables.h>
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#include <ec/google/chromeec/ec.h>
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#include <gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <soc/gpio.h>
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#include "ec.h"
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#define GPIO_PCH_WP GPIO_75
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#define GPIO_EC_IN_RW GPIO_41
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
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{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
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{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{GPIO_EC_IN_RW, ACTIVE_HIGH,
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gpio_get(GPIO_EC_IN_RW), "EC in RW"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_lid_switch(void)
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{
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/* Read lid switch state from the EC. */
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return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
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}
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int get_developer_mode_switch(void)
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{
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/* No physical developer mode switch. It's virtual. */
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return 0;
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}
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int get_recovery_mode_switch(void)
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{
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/* Check if the EC has posted the keyboard recovery event. */
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return !!(google_chromeec_get_events_b() &
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
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}
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int clear_recovery_mode_switch(void)
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{
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/* Clear keyboard recovery event. */
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return google_chromeec_clear_events_b(
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
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}
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int get_write_protect_state(void)
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{
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/* Read PCH_WP GPIO. */
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return gpio_get(GPIO_PCH_WP);
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}
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FLASH 8M {
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WP_RO 4M {
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SI_ALL 2M {
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SI_DESC 4K
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bootblock@509056 32K
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}
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RO_SECTION@2M 2M {
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RO_VPD 0x4000
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FMAP 0x800
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RO_FRID 0x40
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RO_FRID_PAD 0x7c0
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COREBOOT(CBFS)
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# logical boot partition 2. Remove with updated CSE
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SIGN_CSE@0x180000 64K
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# GBB grows to fill the remaining region...
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GBB
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}
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}
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MISC_RW {
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RW_MRC_CACHE 64K
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RW_ELOG 16K
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RW_SHARED 16K {
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SHARED_DATA 8K
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VBLOCK_DEV 8K
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}
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RW_VPD 8K
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}
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RW_SECTION_A 0xf0000 {
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VBLOCK_A 64K
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FW_MAIN_A(CBFS) 768K
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RW_FWID_A 64
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}
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RW_SECTION_B 0xf0000 {
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VBLOCK_B 64K
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FW_MAIN_B(CBFS) 768K
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RW_FWID_B 64
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}
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DEVICE_EXTENSION@7M 1M
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}
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chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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register "pcie_rp4_clkreq_pin" = "0" # wifi/bt
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 on end # - DPTF
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device pci 00.2 on end # - NPK
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device pci 02.0 on end # - Gen
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device pci 03.0 on end # - Iunit
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device pci 0d.0 on end # - P2SB
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device pci 0d.1 on end # - PMC
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device pci 0d.2 on end # - SPI
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device pci 0d.3 on end # - Shared SRAM
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device pci 0e.0 on end # - Audio
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device pci 11.0 on end # - ISH
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device pci 12.0 off end # - SATA
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device pci 13.0 off end # - Root Port 2 - PCIe-A 0
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device pci 13.1 off end # - Root Port 3 - PCIe-A 1
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device pci 13.2 off end # - Root Port 4 - PCIe-A 2
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device pci 13.3 off end # - Root Port 5 - PCIe-A 3
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device pci 14.0 on end # - Root Port 0 - PCIe-B 0 - Wifi
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device pci 14.1 off end # - Root Port 1 - PCIe-B 1
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device pci 15.0 on end # - XHCI
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device pci 15.1 on end # - XDCI
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device pci 16.0 on end # - I2C 0
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device pci 16.1 on end # - I2C 1
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device pci 16.2 on end # - I2C 2
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device pci 16.3 on end # - I2C 3
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device pci 17.0 on end # - I2C 4
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device pci 17.1 on end # - I2C 5
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device pci 17.2 on end # - I2C 6
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device pci 17.3 on end # - I2C 7
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device pci 18.0 on end # - UART 0
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device pci 18.1 on end # - UART 1
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device pci 18.2 on end # - UART 2
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device pci 18.3 on end # - UART 3
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device pci 19.0 on end # - SPI 0
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device pci 19.1 on end # - SPI 1
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device pci 19.2 on end # - SPI 2
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device pci 1a.0 on end # - PWM
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device pci 1b.0 on end # - SDCARD
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device pci 1c.0 on end # - eMMC
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device pci 1e.0 on end # - SDIO
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device pci 1f.0 on # - LPC
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end
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device pci 1f.1 on end # - SMBUS
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end
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end
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x05, // DSDT revision: ACPI v5.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20110725 // OEM revision
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)
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{
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/* global NVS and variables */
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#include <soc/intel/skylake/acpi/globalnvs.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/apollolake/acpi/northbridge.asl>
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#include <soc/intel/apollolake/acpi/southbridge.asl>
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}
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}
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/* Chrome OS specific */
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#include "acpi/chromeos.asl"
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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/* Chipset specific sleep states */
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#include <soc/intel/apollolake/acpi/sleepstates.asl>
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/* Mainboard Specific devices */
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#include "acpi/mainboard.asl"
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}
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/*
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* This file is part of the coreboot project.
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*
|
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* Copyright 2016 Google Inc.
|
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*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
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*/
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#include <arch/acpi.h>
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#include <console/console.h>
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#include <ec/google/chromeec/ec.h>
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#include <rules.h>
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#include <soc/lpc.h>
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#include "ec.h"
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static void ramstage_ec_init(void)
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{
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printk(BIOS_ERR, "mainboard: EC init\n");
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if (acpi_is_wakeup_s3()) {
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google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
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MAINBOARD_EC_S3_WAKE_EVENTS);
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/* Disable SMI and wake events */
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google_chromeec_set_smi_mask(0);
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/* Clear pending events */
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while (google_chromeec_get_event() != 0)
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;
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/* Restore SCI event mask */
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google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
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} else {
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google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
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MAINBOARD_EC_S5_WAKE_EVENTS);
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}
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/* Clear wake event mask */
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google_chromeec_set_wake_mask(0);
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}
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static void bootblock_ec_init(void)
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{
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uint16_t ec_ioport_base;
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size_t ec_ioport_size;
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/*
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* Set up LPC decoding for the ChromeEC I/O port ranges:
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* - Ports 62/66, 60/64, and 200->208
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* - ChromeEC specific communication I/O ports.
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*/
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lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200);
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google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
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lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
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}
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void mainboard_ec_init(void)
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{
|
||||
if (ENV_RAMSTAGE)
|
||||
ramstage_ec_init();
|
||||
else if (ENV_BOOTBLOCK)
|
||||
bootblock_ec_init();
|
||||
}
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_EC_H
|
||||
#define MAINBOARD_EC_H
|
||||
|
||||
#include <ec/google/chromeec/ec_commands.h>
|
||||
|
||||
#define MAINBOARD_EC_SCI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU))
|
||||
|
||||
#define MAINBOARD_EC_SMI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
|
||||
|
||||
/* EC can wake from S5 with lid or power button */
|
||||
#define MAINBOARD_EC_S5_WAKE_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
|
||||
|
||||
/* EC can wake from S3 with lid or power button or key press */
|
||||
#define MAINBOARD_EC_S3_WAKE_EVENTS \
|
||||
(MAINBOARD_EC_S5_WAKE_EVENTS |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
|
||||
|
||||
/* Log EC wake events plus EC shutdown events */
|
||||
#define MAINBOARD_EC_LOG_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
|
||||
|
||||
#ifndef __ACPI__
|
||||
extern void mainboard_ec_init(void);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
};
|
||||
|
||||
/* GPIOs needed prior to ramstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
};
|
||||
|
||||
#endif /* MAINBOARD_GPIO_H */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include <soc/gpio.h>
|
||||
#include "ec.h"
|
||||
#include "gpio.h"
|
||||
|
||||
static void mainboard_init(void *chip_info)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
mainboard_ec_init();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.init = mainboard_init,
|
||||
};
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct lpddr4_swizzle_cfg board_swizzle = {
|
||||
/* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
|
||||
.phys[LP4_PHYS_CH0A] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH0B] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH1A] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH1B] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 },
|
||||
},
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(struct FSPM_UPD *memupd)
|
||||
{
|
||||
struct FSP_M_CONFIG *cfg = &memupd->FspmConfig;
|
||||
|
||||
/* Use a default 2400 speed. */
|
||||
meminit_lpddr4(cfg, LP4_SPEED_2400);
|
||||
/* Enable both logical channels with a 8Gb density. */
|
||||
meminit_lpddr4_enable_channel(cfg, LP4_LCH0, LP4_8Gb_DENSITY,
|
||||
&board_swizzle);
|
||||
meminit_lpddr4_enable_channel(cfg, LP4_LCH1, LP4_8Gb_DENSITY,
|
||||
&board_swizzle);
|
||||
}
|
||||
Loading…
Reference in New Issue