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mb/intel/adlrvp: set power limits dynamically for thermal 

Set power limit values dynamically based on CPU TDP and PCI ID of SKU.
These values are as per platform design specification.

BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board

Change-Id: I8ba901fe7c978aad43b85a860c71b33bfbff2ff5
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet Pawnikar 2021-09-30 09:38:49 +05:30 committed by Felix Held
parent e2e0a6b597
commit e06e43a83f
2 changed files with 11 additions and 6 deletions
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1
src/mainboard/intel/adlrvp/include/baseboard/variants.h
View File

@ -40,6 +40,7 @@ const struct mb_cfg *variant_memory_params(void);
void variant_devtree_update(void); void variant_devtree_update(void);
struct cpu_power_limits { struct cpu_power_limits {
uint16_t mchid; uint16_t mchid;
u8 cpu_tdp;
unsigned int pl1_min_power; unsigned int pl1_min_power;
unsigned int pl1_max_power; unsigned int pl1_max_power;
unsigned int pl2_min_power; unsigned int pl2_min_power;

16
src/mainboard/intel/adlrvp/ramstage.c
View File

@ -10,14 +10,16 @@
#include <soc/soc_chip.h> #include <soc/soc_chip.h>
#include <drivers/intel/dptf/chip.h> #include <drivers/intel/dptf/chip.h>
#include "board_id.h" #include "board_id.h"
#include <intelblocks/power_limit.h>
const struct cpu_power_limits limits[] = { const struct cpu_power_limits limits[] = {
/* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max */ /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max */
/* PL2 values are for performance configuration */ /* PL2 values are for performance configuration */
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000, 55000, 55000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 55000, 55000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 3000, 15000, 55000, 55000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 55000, 55000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000, 64000, 64000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 64000, 64000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 115000, 115000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 64000, 64000 },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000 },
}; };
WEAK_DEV_PTR(dptf_policy); WEAK_DEV_PTR(dptf_policy);
@ -31,8 +33,10 @@ void variant_update_power_limits(void)
uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
u8 tdp = get_cpu_tdp();
for (size_t i = 0; i < ARRAY_SIZE(limits); i++) { for (size_t i = 0; i < ARRAY_SIZE(limits); i++) {
if (mchid == limits[i].mchid) { if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
struct dptf_power_limits *settings = &config->controls.power_limits; struct dptf_power_limits *settings = &config->controls.power_limits;
settings->pl1.min_power = limits[i].pl1_min_power; settings->pl1.min_power = limits[i].pl1_min_power;
settings->pl1.max_power = limits[i].pl1_max_power; settings->pl1.max_power = limits[i].pl1_max_power;