soc/intel/skylake: Use intel/common/xhci driver
Change-Id: I7bd83d293fcc1848f6f64526d8f38d010c1f69a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18223 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -48,6 +48,8 @@ config CPU_SPECIFIC_OPTIONS
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select RTC
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_XHCI
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select SOC_INTEL_COMMON_LPSS_I2C
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select SOC_INTEL_COMMON_NHLT
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select SOC_INTEL_COMMON_RESET
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@ -90,7 +90,6 @@ ramstage-y += tsc_freq.c
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ramstage-y += uart.c
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ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c
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ramstage-y += vr_config.c
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ramstage-y += xhci.c
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smm-y += cpu_info.c
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smm-y += gpio.c
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@ -1,43 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <soc/ramstage.h>
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#include <soc/cpu.h>
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static struct device_operations usb_xhci_ops = {
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.read_resources = &pci_dev_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.ops_pci = &soc_pci_ops,
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};
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static const unsigned short pci_device_ids[] = {
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0x9d2f, /* SunRisePoint LP */
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0xa12f, /* KBL-H*/
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0
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};
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static const struct pci_driver pch_usb_xhci __pci_driver = {
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.ops = &usb_xhci_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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